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參數(shù)資料
| 型號(hào)： | AD7148ACPZ-1REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/57頁 |
| 文件大小： | 0K |
| 描述： | IC CAP-TO-DGTL CONV PROG 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 電容性 |
| 觸摸面板接口： | 2 線 |
| 輸入數(shù)/鍵： | 8 鍵 |
| 分辨率（位）： | 16 b |
| 數(shù)據(jù)接口： | I²C，串行 |
| 數(shù)據(jù)速率/采樣率 (SPS，BPS)： | 250k |
| 電壓基準(zhǔn)： | 內(nèi)部 |
| 電源電壓： | 2.6 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP |
| 包裝： | 帶卷 (TR) |
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AD7148
Rev. A | Page 15 of 56
Table 9. CDC Conversion Times for Full Power Mode
SEQUENCE_STAGE_NUM
Conversion Time (ms)
Decimation = 64
Decimation = 128
Decimation = 256
0
0.768
1.536
3.072
1
1.536
3.072
6.144
2
2.304
4.608
9.216
3
3.072
6.144
12.288
4
3.84
7.68
15.36
5
4.608
9.216
18.432
6
5.376
10.752
21.504
7
6.144
12.288
24.576
Full Power Mode CDC Conversion Sequence Time
The full power mode CDC conversion sequence time for all eight
stages is set by configuring the SEQUENCE_STAGE_NUM
and DECIMATION bits, as outlined in Table 9.
Figure 23 shows a simplified timing diagram of the full power
CDC conversion time. The full power mode CDC conversion
tCONV_FP
CONVERSION
SEQUENCE N
CONVERSION
SEQUENCE N+1
CONVERSION
SEQUENCE N+2
CDC
CONVERSION
07
15
5-
02
2
Figure 23. Full Power Mode CDC Conversion Sequence Time
Low Power Mode CDC Conversion Sequence Time
with Delay
The frequency of each CDC conversion, while operating in the
low power automatic wake-up mode, is controlled by using the
LP_CONV_DELAY bits located at Address 0x000[3:2], in addi-
tion to the registers listed in Table 9. This feature provides some
flexibility for optimizing the conversion time to meet system
requirements vs. AD7148 power consumption.
For example, maximum power savings is achieved when the
LP_CONV_DELAY bits (Address 0x000[3:2] are set to 11. With
a setting of 11, the AD7148 automatically wakes up, performing
a conversion every 800 ms.
Table 10. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits
Delay Between Conversions (ms)
00
200
01
400
10
600
11
800
Figure 24 shows a simplified timing example of the low power
CDC conversion time. As shown, the low power CDC conversion
time is set by tCONV_FP and the LP_CONV_DELAY bits.
0
715
5-
0
23
CONVERSION
SEQUENCE N
CDC
CONVERSION
SEQUENCE N+1
LP_CONV_DELAY
tCONV_LP
tCONV_FP
Figure 24. Low Power Mode CDC Conversion Sequence Time
CDC CONVERSION RESULTS
Certain high resolution sensors require the host to read back
the CDC conversion results for processing. The registers required
for host processing are located in the Bank 3 registers. The host
processes the data readback from these registers using a software
algorithm to determine position information.
In addition to the results registers found in the Bank 3 registers,
the AD7148 provides the 16-bit CDC output data directly, starting
at Address 0x00B of the Bank 1 registers. Reading back the CDC
16-bit conversion data register allows for customer-specific appli-
cation data processing.
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