參數(shù)資料
型號： AD7148ACPZ-1REEL
廠商： Analog Devices Inc
文件頁數(shù)： 37/57頁
文件大?。?/td> 0K
描述： IC CAP-TO-DGTL CONV PROG 16LFCSP
標準包裝： 5,000
類型： 電容性
觸摸面板接口： 2 線
輸入數(shù)/鍵： 8 鍵
分辨率（位）： 16 b
數(shù)據(jù)接口： I²C，串行
數(shù)據(jù)速率/采樣率 (SPS，BPS)： 250k
電壓基準： 內(nèi)部
電源電壓： 2.6 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP
包裝： 帶卷 (TR)
AD7148
Rev. A | Page 41 of 56
Table 26. STAGEx_HIGH_LIMIT_INT Register1
Address
Data
Bit
Default
Value
Type
Mnemonic
Description
0x009
[0]
0
R
STAGE0_HIGH_LIMIT_INT
STAGE0 CDC conversion high limit interrupt result
1 = indicates STAGE0_HIGH_THRESHOLD value exceeded
[1]
0
R
STAGE1_HIGH_LIMIT_INT
STAGE1 CDC conversion high limit interrupt result
1 = indicates STAGE1_HIGH_THRESHOLD value exceeded
[2]
0
R
STAGE2_HIGH_LIMIT_INT
Stage2 CDC conversion high limit interrupt result
1 = indicates STAGE2_HIGH_THRESHOLD value exceeded
[3]
0
R
STAGE3_HIGH_LIMIT_INT
STAGE3 CDC conversion high limit interrupt result
1 = indicates STAGE3_HIGH_THRESHOLD value exceeded
[4]
0
R
STAGE4_HIGH_LIMIT_INT
STAGE4 CDC conversion high limit interrupt result
1 = indicates STAGE4_HIGH_THRESHOLD value exceeded
[5]
0
R
STAGE5_HIGH_LIMIT_INT
STAGE5 CDC conversion high limit interrupt result
1 = indicates STAGE5_HIGH_THRESHOLD value exceeded
[6]
0
R
STAGE6_HIGH_LIMIT_INT
STAGE6 CDC conversion high limit interrupt result
1 = indicates STAGE6_HIGH_THRESHOLD value exceeded
[7]
0
R
STAGE7_HIGH_LIMIT_INT
STAGE7 CDC conversion high limit interrupt result
1 = indicates STAGE7_HIGH_THRESHOLD value exceeded
[15:8]
Unused
Set unused register bits to 0
1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Table 27. STAGEx_COMPLETE_INT_STATUS Register1
Address
Data
Bit
Default
Value
Type
Mnemonic
Description
0x00A
[0]
0
R
STAGE0_COMPLETE_INT_STATUS
STAGE0 conversion complete register interrupt status
1 = indicates STAGE0 conversion completed
[1]
0
R
STAGE1_COMPLETE_INT_STATUS
STAGE1 conversion complete register interrupt status
1 = indicates STAGE1 conversion completed
[2]
0
R
STAGE2_COMPLETE_INT_STATUS
STAGE2 conversion complete register interrupt status
1 = indicates STAGE2 conversion completed
[3]
0
R
STAGE3_COMPLETE_INT_STATUS
STAGE3 conversion complete register interrupt status
1 = indicates STAGE3 conversion completed
[4]
0
R
STAGE4_COMPLETE_INT_STATUS
STAGE4 conversion complete register interrupt status
1 = indicates STAGE4 conversion completed
[5]
0
R
STAGE5_COMPLETE_INT_STATUS
STAGE5 conversion complete register interrupt status
1 = indicates STAGE5 conversion completed
[6]
0
R
STAGE6_COMPLETE_INT_STATUS
STAGE6 conversion complete register interrupt status
1 = indicates STAGE6 conversion completed
[7]
0
R
STAGE7_COMPLETE_INT_STATUS
STAGE7 conversion complete register interrupt status
1 = indicates STAGE7 conversion completed
[15:8]
Unused
Set unused register bits to 0
1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.
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