參數(shù)資料
型號(hào)： AD7142ACPZ-500RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 41/73頁(yè)
文件大?。?/td> 0K
描述： IC CAP-TO-DGTL CONV PROG 32LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 電容數(shù)字轉(zhuǎn)換器
分辨率（位）： 16 b
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 2.6 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD7142ACPZ-500RL7DKR
AD7142
Rev. A | Page 45 of 72
Table 26. STAGE_COMPLETE_INT_EN Register
Address
Data Bit
Default Value
Type
Name
Description
0x007
[0]
0
R/W
STAGE0_COMPLETE_EN
STAGE0 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE0 conversion
[1]
0
STAGE1_COMPLETE_EN
STAGE1 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE1 conversion
[2]
0
STAGE2_COMPLETE_EN
STAGE2 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE2 conversion
[3]
0
STAGE3_COMPLETE_EN
STAGE3 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE3 conversion
[4]
0
STAGE4_COMPLETE_EN
STAGE4 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE4 conversion
[5]
0
STAGE5_COMPLETE_EN
STAGE5 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE5 conversion
[6]
0
STAGE6_COMPLETE_EN
STAGE6 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE6 conversion
[7]
0
STAGE7_COMPLETE_EN
STAGE7 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE7 conversion
[8]
0
STAGE8_COMPLETE_EN
STAGE8 conversion complete interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE8 conversion
[9]
0
STAGE9_COMPLETE_EN
STAGE9 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE9 conversion
[10]
0
STAGE10_COMPLETE_EN
STAGE10 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE10 conversion
[11]
0
STAGE11_COMPLETE_EN
STAGE11 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE11 conversion
[12]
0
GPIO_INT_EN
Interrupt control when GPIO input pin changes level
0 = disabled
1 = enabled
[15:13]
Unused
Set unused register bits = 0
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