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參數(shù)資料
| 型號： | AD7142ACPZ-500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CAP-TO-DGTL CONV PROG 32LFCSP |
| 標準包裝： | 1 |
| 類型： | 電容數(shù)字轉換器 |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 單電源 |
| 電源電壓： | 2.6 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD7142ACPZ-500RL7DKR |
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AD7142
Rev. A | Page 26 of 72
INTERRUPT OUTPUT
The AD7142 has an interrupt output that triggers an interrupt
service routine on the host processor. The INT signal is on
Pin 25, and is an open-drain output. There are three types of
interrupt events on the AD7142: a CDC conversion complete
interrupt, a sensor threshold interrupt, and a GPIO interrupt.
Each interrupt has enable and status registers. The conversion
complete and sensor threshold interrupts can be enabled on a
per conversion stage basis. The status registers indicate what
type of interrupt triggered the INT pin. Status registers are
cleared, and the INT signal is reset high, during a read
operation. The signal returns high as soon as the read address
has been set up.
CDC CONVERSION COMPLETE INTERRUPT
The AD7142 interrupt signal asserts low to indicate the
completion of a conversion stage, and new conversion result
data is available in the registers.
The interrupt can be independently enabled for each conversion
stage. Each conversion stage complete interrupt can be enabled via
the STAGE_COMPLETE_EN register (Address 0x007). This
register has a bit that corresponds to each conversion stage. Setting
this bit to 1 enables the interrupt for that stage. Clearing this bit to 0
disables the conversion complete interrupt for that stage.
In normal operation, the AD7142 interrupt is enabled only for the
last stage in a conversion sequence. For example, if there are five
conversion stages, the conversion complete interrupt for STAGE4 is
enabled. INT only asserts when all five conversion stages are
complete, and the host can read new data from all five result
registers. The interrupt is cleared by reading the STAGE_
COMPLETE_STATUS_INT register located at Address 0x00A.
Register 0x00A is the conversion complete interrupt status
register. Each bit in this register corresponds to a conversion
stage. If a bit is set, it means that the conversion complete
interrupt for the corresponding stage was triggered. This
register is cleared on a read, provided the underlying condition
that triggered the interrupt has gone away.
SENSOR TOUCH INTERRUPT
Use the sensor touch interrupt mode to interrupt the host
processor only when the sensor is activated.
Configuring the AD7142 into this mode results in the interrupt
being asserted when the user makes contact with the sensor and
again when the user lifts off the sensor. The second interrupt is
required to alert the host processor that the user is no longer
contacting the sensor.
The registers located at Address 0x005 and Address 0x006 are
used to enable the interrupt output for each stage. The registers
located at Address 0x008 and Address 0x009 are used to read
back the interrupt status for each stage.
Figure 38 shows the interrupt output timing during contact with
one of the sensors connected to STAGE0 when operating in the
sensor touch interrupt mode. For a low limit configuration, the
interrupt output is asserted as soon as the sensor is contacted and
again after the user has stopped contacting the sensor.
Note: The interrupt output remains low until the host processor
reads back the interrupt status registers located at Address 0x008
and Address 0x009.
The interrupt output is asserted when there is a change in the
threshold status bits. This could indicate that a user is now
touching the sensor(s) for the first time, the number of sensors
being touched has changed, or the user is no longer touching
the sensor(s). Reading the status bits in the interrupt status
register shows the current sensor activations.
4
2
CONVERSION
STAGE
SERIAL
READBACK
NOTES:
1. USER TOUCHING DOWN ON SENSOR
2. ADDRESS 0X008 READ BACK TO CLEAR INTERRUPT
3. USER LIFTING OFF OF SENSOR
4. ADDRESS 0X008 READ BACK TO CLEAR INTERRUPT
STAGE0
STAGE1
INT OUTPUT
05702-
055
Figure 38. Example of Sensor Touch Interrupt
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7142ACPZ-500RL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Controller for Capacitance Touch Sensors |
| AD7142ACPZ-REEL | 功能描述:IC CAP-TO-DGTL CONV PROG 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD7142ACPZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Controller for Capacitance Touch Sensors |
| AD7143 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Controller for Capacitance Touch Sensors |
| AD7143ACPZ | 制造商:Analog Devices 功能描述:IC CDC 16BIT SMD LFCSP-16 7143 制造商:Analog Devices 功能描述:IC, CDC, 16BIT, SMD, LFCSP-16, 7143 |
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