- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1891 > AD7142ACPZ-500RL7 (Analog Devices Inc)IC CAP-TO-DGTL CONV PROG 32LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD7142ACPZ-500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/73頁 |
| 文件大小： | 0K |
| 描述： | IC CAP-TO-DGTL CONV PROG 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 電容數(shù)字轉(zhuǎn)換器 |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 單電源 |
| 電源電壓： | 2.6 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD7142ACPZ-500RL7DKR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
AD7142
Rev. A | Page 25 of 72
Σ-Δ
16-BIT
CDC
16
STAGE_MAX_WORD0
STAGE_MAX_WORD1
STAGE_MAX_WORD2
STAGE_MAX_WORD3
STAGE_MIN_WORD0
STAGE_MIN_WORD1
STAGE_MIN_WORD2
STAGE_MIN_WORD3
STAGE_MAX_AVG
BANK 3 REGISTERS
STAGE_HIGH_THRESHOLD
BANK 3 REGISTERS
STAGE_MAX_TEMP
BANK 3 REGISTERS
MAX LEVEL
DETECTION
LOGIC
STAGE_MIN_AVG
BANK 3 REGISTER3
STAGE_LOW_THRESHOLD
BANK 3 REGISTERS
STAGE_MIN_TEMP
BANK 3 REGISTERS
BANK 3
REGISTERS
BANK 3
REGISTERS
05
70
2-
06
2
MIN LEVEL
DETECTION
LOGIC
Figure 37. Tracking the Minimum and Maximum Average Sensor Values
Table 13. Additional Information about Environmental Calibration and Adaptive Threshold Registers
Register
Location
Description
NEG_THRESHOLD_SENSITIVITY
Bank 2
Used in Equation 2. This value is programmed once at start up.
NEG_PEAK_DETECT
Bank 2
Used by internal adaptive threshold logic only.
The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value, and the min average CDC value. If the output of the CDC gets within the
NEG_PEAK_DETECT percentage of the min average, only then is the min average value
updated.
POS_THRESHOLD_SENSITIVITY
Bank 2
Used in Equation 1. This value is programmed once at start up.
POS_PEAK_DETECT
Bank 2
Used by internal adaptive threshold logic only.
The POS_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value, and the max average CDC value. If the output of the CDC gets within the
POS_PEAK_DETECT percentage of the min average, only then is the max average value
updated.
STAGE_OFFSET_LOW
Bank 2
Used in Equation 2. An initial value (based on sensor characterization) is programmed
into this register at start up. The AD7142 on chip calibration algorithm automatically
updates this register based on the amount of sensor drift due to changing ambient
conditions. Set to 80% of the STAGE_OFFSET_LOW_CLAMP value.
STAGE_OFFSET_HIGH
Bank 2
Used in Equation 1. An initial value (based on sensor characterization) is programmed
into this register at start up. The AD7142 on chip calibration algorithm automatically
updates this register based on the amount of sensor drift due to changing ambient
conditions. Set to 80% of the STAGE_OFFSET_HIGH_CLAMP value.
STAGE_OFFSET_HIGH_CLAMP
Bank 2
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at
start up. The value in this register prevents a user from causing a sensor’s output value
to exceed the expected nominal value.
Set to the maximum expected sensor response, maximum change in CDC output code .
STAGE_OFFSET_LOW_CLAMP
Bank 2
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at
start up. The value in this register prevents a user from causing a sensor’s output value
to exceed the expected nominal value.
Set to the minimum expected sensor response, minimum change in CDC output code .
STAGE_SF_AMBIENT
Bank 3
Used in Equation 1 and Equation 2. This is the ambient sensor output, when the sensor
is not touched, as calculated using the slow FIFO.
STAGE_HIGH_THRESHOLD
Bank 3
Equation 1 value.
STAGE_LOW_THRESHOLD
Bank 3
Equation 2 value.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7143ACPZ-1REEL | IC CONV CAP-TO-DGTL PROG 16LFCSP |
| AD7147A-1ACBZ500R7 | IC CDC 13CH I2C W/RAM 25WLCSP |
| AD7147WPACPZ-1500R | IC CAP-TO-DGTL CONV PROG 24LFCSP |
| AD7150BRMZ-REEL | IC CAP CONV 2CH ULT LP 10MSOP |
| AD7151BRMZ-REEL | IC CAP CONV 1CH ULT LP 10MSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7142ACPZ-500RL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Controller for Capacitance Touch Sensors |
| AD7142ACPZ-REEL | 功能描述:IC CAP-TO-DGTL CONV PROG 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD7142ACPZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Controller for Capacitance Touch Sensors |
| AD7143 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Controller for Capacitance Touch Sensors |
| AD7143ACPZ | 制造商:Analog Devices 功能描述:IC CDC 16BIT SMD LFCSP-16 7143 制造商:Analog Devices 功能描述:IC, CDC, 16BIT, SMD, LFCSP-16, 7143 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。