參數(shù)資料
型號： AD7142ACPZ-500RL7
廠商： Analog Devices Inc
文件頁數(shù)： 30/73頁
文件大小： 0K
描述： IC CAP-TO-DGTL CONV PROG 32LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 電容數(shù)字轉(zhuǎn)換器
分辨率（位）： 16 b
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 2.6 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD7142ACPZ-500RL7DKR
AD7142
Rev. A | Page 35 of 72
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB X's ARE DON'T CARE BITS.
5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB X’s ARE DON’T CARE BITS.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BITS.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
SDA
DEV
A6
DEV
A5
DEV
A4
R/W
A7
A6
SCLK
DEV
A3
A1
A0
1
26
23
4
17
18
19
20
25
DEV
A2
DEV
A1
DEV
A0
ACK
A15
A14
11
16
56
78
910
START
AD7142-1 DEVICE ADDRESS
A9
A8
REGISTER ADDRESS[A15:A8]
REGISTER ADDRESS[A7:A0]
ACK
35
28
30
34
37
36
44
38
45
D1
D0
D7
D6
REGISTER DATA[D7:D0]
SR
ACK
46
P
DEV
A6
DEV
A5
DEV
A4
1
23
t8
t7
t6
t
5
t4
t2
t1
t3
AD7142 DEVICE ADDRESS
ACK
27
AD7142-1 DEVICE ADDRESS
DEV
A6
DEV
A5
DEV
A1
DEV
A0
05702-
038
R/W
29
39
35
28
30
34
37
36
44
38
45
D1
D0
D7
D6
REGISTER DATA[D7:D0]
S
ACK
46
P
t
5
t4
AD7142-1 DEVICE ADDRESS
DEV
A6
DEV
A5
DEV
A1
DEV
A0
R/W
29
39
P
USING
REPEATED START
SEPARATE READ AND
WRITE TRANSACTIONS
ACK
Figure 51. Example of I2C Timing for Single Register Readback Operation
AC
K
WRITE
OUTPUT FROM MASTER
OUTPUT FROM AD7142
S
P
AC
K
6-BIT DEVICE
ADDRESS
S = START BIT
P = STOP BIT
SR = REPEATED START BIT
ACK = ACKNOWLEDGE BIT
ACK = NO ACKNOWLEDGE BIT
REGISTER ADDR
[15:8]
REGISTER ADDR
[7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
AC
K
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
AC
K
W
AC
K
AC
K
AC
K
AC
K
READ (USING REPEATED START)
S
AC
K
6-BIT DEVICE
ADDRESS
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
AC
K
W
AC
K
AC
K
READ DATA
LOW BYTE [7:0]
057
02-
03
9
R
SR
P
AC
K
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
AC
K
READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS)
S
AC
K
6-BIT DEVICE
ADDRESS
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
AC
K
W
AC
K
AC
K
READ DATA
LOW BYTE [7:0]
R
P
S
ACK
Figure 52. Example of Sequential I2C Write and Readback Operation
VDRIVE INPUT
The supply voltage to all pins associated with both the I2C and
SPI serial interfaces (SDO, SDI, SCLK, SDA, and CS) is separate
from the main VCC supplies and is connected to the VDRIVE pin.
This allows the AD7142 to be connected directly to processors
whose supply voltage is less than the minimum operating
voltage of the AD7142 without the need for external level-
shifters. The VDRIVE pin can be connected to voltage supplies as
low as 1.65 V and as high as DVCC.
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