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參數(shù)資料
| 型號(hào)： | AD6641BCPZRL7-500 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC IF RCVR 11BIT 200MSPS 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 應(yīng)用： | 無線通信系統(tǒng) |
| 接口： | CMOS，LVDS，并聯(lián)， 串行，SPI |
| 電源電壓： | 1.8 V ~ 2 V |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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AD6641
Rev. 0 | Page 24 of 28
SPORT Master Mode (Single Capture)
Details of the transaction diagram for serial master mode are
shown in Figure 39 for single capture mode with the SDO
output. Clock cycles are approximate because the fill and dump
signals can be driven asynchronously. In this example, SCLK is
derived from the master clock with a divide by 8 programmed
from the SPI.
Fill Pulse (1)
The FIFO captures data after a fill signal (high level) is detected
on the rising edge of the sampling clock. In synchronous opera-
tion, a valid high level is accomplished by adhering to the setup
and hold times specified. For nonsynchronous control, the fill
signal can be widened to accommodate two or more clock
cycles to guarantee capture of a high level. Fill count (0x104) is
reset on the rising edge of the clock and is incremented on
subsequent clock cycles only after the fill signal returns low.
A new fill signal at any point during the capture resets the
counter and begins filling the FIFO.
Empty Signal (2)
After the FIFO state machine has begun loading data, the empty
signal goes low 24 clock cycles after the fill signal was last
sampled high.
Full Signal (3)
The full signal indicates when the FIFO has been filled and is
driven high when the number of samples specified has been
captured in the FIFO, where
Number of Samples = (FILL_CNT + 1) × 64
The time at which the full signal goes high is based on
(FILL_CNT + 1) × 64 + 13 clock cycles after the fill signal was
last sampled high.
Dump Signal (4)—Transition to High
The dump signal initiates reading data from the FIFO. Dump is
enabled with a high level and should be initiated only after the
full signal goes high. The dump signal should be held high until
all data has been read out of the FIFO.
SCLK Signal (5)
The SCLK (serial clock) signal is configured as an output from
the device when in the master mode of operation. SCLK begins
cycling five ADC clock cycles after the dump signal is sampled
high and continues cycling up until one additional cycle after
the empty signal goes high. SCLK then remains low until the
next dump operation.
SDFS Signal (6)
The SDFS (serial data frame sync) signal is configured as an
output from the device when in the master mode of operation.
Frame synchronization begins 15 ADC clock cycles after the
dump signal is sampled.
Dump Signal (7)—Transition to Low
A dump signal transition to low is applied after data has been
read out of the FIFO.
Empty Signal (8)—Transition to High
The empty signal transitions to high after data has been output
from the FIFO based on the clock cycle count of (FILL_CNT +
1) × 64.
The transition occurs 76 ADC clock cycles after the last LSB(s)
of data have been output on the serial port.
FILL
1
2
3
4
5
6
7
8
EMPTY
FULL
DUMP
SCLK
SDFS
SDO
09
81
3-0
37
Figure 39. SPORT Master Mode Transaction Diagram
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| AD6642BBCZ | 功能描述:IC IF RCVR 11BIT 200MSPS 144BGA RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:* |
| AD6642BBCZRL | 功能描述:IC IF RCVR 11BIT 200MSPS 144BGA RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:* |
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