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參數(shù)資料
| 型號： | AD6641BCPZRL7-500 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC IF RCVR 11BIT 200MSPS 56LFCSP |
| 標準包裝： | 750 |
| 應用： | 無線通信系統(tǒng) |
| 接口： | CMOS，LVDS，并聯(lián)， 串行，SPI |
| 電源電壓： | 1.8 V ~ 2 V |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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AD6641
Rev. 0 | Page 20 of 28
SPI REGISTER MAP
Table 10. Memory Map Register
Addr.
(Hex)
Parameter Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00
CHIP_PORT_CONFIG
0
LSB
first
Soft
reset
1
Soft
reset
LSB first
0
0x18
The nibbles
should be
mirrored by
the user so
that LSB or
MSB first
mode
registers
correctly,
regardless of
shift mode.
0x01
CHIP_ID
8-bit chip ID, Bits[7:0] = 0xA0
Read
only
Default is
unique chip
ID, different
for each
device. This is
a read-only
register.
0x02
CHIP_GRADE
0
Speed grade:
10 = 500 MSPS
X
Read
only
Child ID
used to
differentiate
graded
devices.
Transfer Register
0xFF
DEVICE_UPDATE
[7:1] = 0000000
SW
transfer
0x00
Synchro-
nously
transfers data
from the
master shift
register to the
slave.
ADC Functions
0x08
Modes
0
Internal power-down mode:
000 = normal (power-up, default)
001 = full power-down
010 = standby
011 = reserved
0x00
Determines
various
generic
modes of chip
operation.
0x0D
TEST_IO
(For user-defined
mode only, set
Bits[3:0] = 1000)
00 = Pattern 1 only
01 = toggle
Pattern 1/
Pattern 2
10 = toggle
Pattern 1/0000
11 = toggle
Pattern 1/
Pattern 2/0000
Reset
PN23
gen:
1 = on
0 = off
(default)
Reset
PN9
gen: 1 =
on
0 = off
(default)
Output test mode:
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = FS short
0100 = checkerboard output
0101 = PN23 sequence
0110 = PN9
0111 = one/zero word toggle
1000 = user defined
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(format determined by OUTPUT_MODE)
0x00
When set, the
test data is
placed on the
output pins in
place of
normal data.
Set pattern
values:
Pattern 1:
Reg 0x19,
Reg 0x1A
Pattern 2:
Reg 0x1B
Reg 0x1C.
0x14
OUTPUT_MODE
0
Output
disable:
0 =
enable
(default)
1 =
disable
0 =
CMOS:
1 =
LVDS
(default)
Output
invert:
1 = on
0 = off
(default)
Data format select:
00 = offset binary
(default)
01 = twos
complement
10 = Gray code
11 = reserved
0x08
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