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參數(shù)資料
型號： AD5757ACPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 42/44頁
文件大?。?/td> 0K
描述： IC DAC 16BIT QUAD IOUT 64LFCSP
標準包裝： 750
設(shè)置時間： 15µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： *
采樣率（每秒）： *
Data Sheet
AD5757
Rev. D | Page 7 of 44
AC PERFORMANCE CHARACTERISTICS
AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 ; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Current Output
Output Current Settling Time
15
s
To 0.1% FSR (0 mA to 24 mA)
See test conditions/
comments
ms
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
0.15
LSB p-p
16-bit LSB, 0 mA to 24 mA range
Output Noise Spectral Density
0.5
nA/√Hz
Measured at 10 kHz, midscale output, 0
mA to 24 mA range
1 Guaranteed by design and characterization; not production tested.
TIMING CHARACTERISTICS
AVDD = VBOOST_x= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 ; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
Limit at T
MIN, TMAX
Unit
Description
t
1
33
ns min
SCLK cycle time
t
2
13
ns min
SCLK high time
t
3
13
ns min
SCLK low time
t
4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t
5
13
ns min
24th/32nd SCLK falling edge to SYNC rising edge (see Figure 54)
t
6
198
ns min
SYNC high time
t
7
5
ns min
Data setup time
t
8
5
ns min
Data hold time
t
9
20
s min
SYNC rising edge to LDAC falling edge (all DACs updated or any channel has
digital slew rate control enabled)
5
s min
SYNC rising edge to LDAC falling edge (single DAC updated)
t
10
ns min
LDAC pulse width low
t
11
500
ns max
LDAC falling edge to DAC output response time
t
12
s max
DAC output settling time
t
13
10
ns min
CLEAR high time
t
14
5
s max
CLEAR activation time
t
15
40
ns max
SCLK rising edge to SDO valid
t
16
21
s min
SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated)
5
s min
SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated)
t
17
500
ns min
LDAC falling edge to SYNC rising edge
t
18
800
ns min
RESET pulse width
t
19
20
s min
SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated)
5
s min
SYNC high to next SYNC low (digital slew rate control disabled) (single DAC
updated)
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with t
RISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
4 This specification applies if LDAC is held low during the write cycle; otherwise, see t
9.
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