
Data Sheet
AD5757
Rev. D | Page 11 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DG
ND
R
ESE
T
AV
DD
NC
C
HART
A
IG
A
T
E
A
CO
M
P
DC
_
A
V
B
OOS
T
_
A
NC
I OU
T
_
A
AG
ND
NC
C
HART
B
NC
IG
A
T
E
B
CO
M
P
DC
_
B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
R
SE
T
_
C
R
SE
T
_
D
RE
F
O
UT
RE
F
IN
NC
CHART
D
IGA
T
E
D
CO
M
P
DC
_
D
V
B
OOS
T
_
D
NC
I OU
T
_
D
AG
ND
NC
CHART
C
NC
IGA
T
E
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RSET_B
RSET_A
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DVDD
DGND
LDAC
CLEAR
ALERT
FAULT
COMPDCDC_C
IOUT_C
VBOOST_C
AVCC
SWC
GNDSWC
GNDSWD
SWD
AGND
SWA
GNDSWA
GNDSWB
SWB
AGND
VBOOST_B
IOUT_B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD5757
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD SHOULD BE CONNECTED TO AGND, OR ALTERNATIVELY,
IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT
THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
092
25-
0
06
Figure 7. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RSET_B
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_B
2
RSET_A
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_A
3, 4
REFGND
Ground Reference Point for Internal Reference.
5
AD0
Address Decode for the Device Under Test (DUT) on the Board.
6
AD1
Address Decode for the DUT on the Board. It is not recommended to tie both AD1 and AD0 low when using PEC,
7
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
8
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at
clock speeds of up to 30 MHz.
9
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
10
SDO
11
DVDD
Digital Supply. The voltage range is from 2.7 V to 5.5 V.
12, 17
DGND
Digital Ground.
13
LDAC
Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When
tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held
high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at
the falling edge of LDAC
(see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The
LDAC pin must not be left unconnected.
14
CLEAR
Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed
information. When CLEAR is active, the DAC output register cannot be written to.