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參數(shù)資料
| 型號(hào)： | AD571JD |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT MONO W/CLK 18-CDIP |
| 產(chǎn)品變化通告： | Redesign Change 26/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 25k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 18-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 18-CDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
AD571
REV.
–7–
Figure 13. Sample-Hold Interface to the AD571
INTERFACING THE AD571 TO A MICROPROCESSOR
The AD571 can easily be arranged to be driven from standard
microprocessor control lines and to present data to any standard
microprocessor bus (4-, 8-, 12- or 16-bit) with a minimum of
additional control components. The configuration shown in
Figure 14 is designed to operate with an 8-bit bus and standard
8080 control signals.
Figure 14. Interfacing AD571 to an 8-Bit Bus
(8080 Control Structure)
The input control circuitry shown is required to ensure that the
AD571 receives a sufficiently long B &
C input pulse. When the
converter is ready to start a new conversion, the B &
C line is
low, and
DR is low. To command a conversion, the start ad-
dress decode line goes low, followed by
WR. The B & C line
will now go high, followed about 1.5
μs later by DR. This resets
the external flip-flop and brings B &
C back to low, which ini-
tiates the conversion cycle. At the end of the conversion cycle,
the
DR line goes low, the data outputs will become active with
the new data and the control lines will return to the standby
state. The 100 pF capacitor slows down the
DR line enough to
be used as a latch signal for data outputs. The new data will
remain active until a new conversion is commanded. The self-
pulsing nature of this circuit guarantees a sufficient convert
pulse width.
This new data can now be presented to the data bus by en-
abling the three-state buffers when desired. A data word
(8-bit or 2-bit) is loaded onto the bus when its decoded ad-
dress goes low and the
RD line goes low. This arrangement
presents data to the bus “l(fā)eft-justified,” with the highest bits in
the 8-bit word; a “right-justified” data arrangement can be set
up by a simple re-wiring. Polling the converter to determine if
conversion is complete can be done by addressing the gate
which buffers the
DR line, as shown. In this configuration, there
is no need for additional buffer register storage: the data can be
held indefinitely in the AD571, since the B &
C line is continu-
ally held low.
BUS INTERFACING WITH A PERIPHERAL INTERFACE
CIRCUIT
An improved technique for interfacing to a
μP bus involves the
use of special peripheral interfacing circuits (or I/O devices),
such as the MC6821 Peripheral Interface Adapter (PIA). Shown
in Figure 15 is a straightforward application of a PIA to multi-
plex up to 8 AD571 circuits. The AD571 has 3-state outputs,
Figure 15. Multiplexing 8 AD571s Using Single PIA for
μP Interface. No Other Logic Required (6800 Control
Structure)
hence the data bit outputs can be paralleled, provided that only
one converter at a time is permitted to be the active state. The
DATA READY output of the AD571 is an open collector with
resistor pull-up, thus several
DR lines can be wire-ored to
allow indication of the status of the selected device. One of the
8-bit ports of the PIA is combined with 2 bits from the other
port and programmed as a 10-bit input port. The remaining 6
bits of the second port are programmed as outputs and along
B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD571JD/+ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD571K | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit A/D Converter |
| AD571KD | 制造商:Analog Devices 功能描述:ADC Single SAR 10-bit Parallel 18-Pin SBCDIP |
| AD571KD/+ | 制造商:Analog Devices 功能描述:ADC SGL SAR 10-BIT PARALLEL 18PIN SBCDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:IC, MONO 10-BIT A/D CONV - Bulk |
| AD571S | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit A/D Converter |
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