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參數(shù)資料
| 型號： | AD1846JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 277K |
| 代理商： | AD1846JP |
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AD1846
REV. A
–7–
PIN DE SCRIPT ION
Parallel Interface
Pin Name
PLCC
I/O
Description
CDRQ
12
O
Capture Data Request. T he assertion of this signal indicates that the Codec has a captured
audio sample from the ADC ready for transfer. T his signal will remain asserted until all the
bytes from the capture buffer have been transferred.
Capture Data Acknowledge. T he assertion of this active LO signal indicates that the
RD
cycle occurring is a DMA read from the capture buffer.
Playback Data Request. T he assertion of this signal indicates that the Codec is ready for
more DAC playback data. T he signal will remain asserted until all the bytes needed for a
playback sample have been transferred.
Playback Data Acknowledge. T he assertion of this active LO signal indicates that the
WR
cycle occurring is a DMA write to the playback buffer.
Codec Addresses. T hese address pins are asserted by the Codec interface logic during a con-
trol register/PIO access. T he state of these address lines determine which register is accessed.
Read Command Strobe. T his active LO signal defines a read cycle from the Codec. T he
cycle may be a read from the control/PIO registers, or the cycles could be a read from the
Codec’s DMA sample registers.
Write Command Strobe. T his active LO signal indicates a write cycle to the Codec. T he
cycle may be a write to the control/PIO registers, or the cycle could be a write to the Codec’s
DMA sample registers.
AD1846 Chip Select. T he Codec will not respond to any control/PIO cycle accesses unless
this active LO signal is LO. T his signal is ignored during DMA transfers.
Data Bus. T hese pins transfer data and control information between the Codec and the host.
CDAK
11
I
PDRQ
14
O
PDAK
13
I
ADR1:0
9 & 10
I
RD
60
I
WR
61
I
CS
59
I
DAT A7:0
3–6 &
65–68
63
I/O
DBEN
O
Data Bus Enable. T his pin enables the external bus drivers. T his signal is normally HI.
For control register/PIO cycles,
DBEN
= (
WR
OR
RD
) AND
CS
For DMA cycles,
DBEN
= (
WR
OR
RD
) AND (
PDAK
OR
CDAK
)
Data Bus Direction. T his pin controls the direction of the data bus transceiver. HI enables
writes from the host to the AD1846; LO enables reads from the AD1846 to the host bus.
T his signal is normally HI.
For control register/PIO cycles,
DBDIR =
RD
AND
CS
For DMA cycles,
DBDIR =
RD
AND (
PDAK
OR
CDAK
)
DBDIR
62
O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1846JP-REEL | 制造商:Analog Devices 功能描述: |
| AD1847 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundPort Stereo Codec |
| AD1847JP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| AD1847JST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundPort Stereo Codec |
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