- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375230 > AD1846JP (ANALOG DEVICES INC) Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec PDF資料下載
參數(shù)資料
| 型號： | AD1846JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 277K |
| 代理商： | AD1846JP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD1846
REV. A
–21–
DAT A AND CONT ROL T RANSFE RS
T he AD1846 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control reg-
ister accesses and for applications lacking DMA control. PIO
transfers can be made on one channel while the other is per-
forming DMA. T ransfers to and from the AD1846 SoundPort
Codec are asynchronous relative to the internal data conversion
clock. T ransfers are buffered, but the AD1846 supports no in-
ternal FIFOs. T he host is responsible for providing playback
data before the next digital-to-analog conversion and removing
capture data before the next analog-to-digital conversion.
Data Ordering
T he number of byte-wide transfers required depends on the
data format selected. T he AD1846 is designed for “l(fā)ittle
endian” formats in which the least significant byte (i.e., occupy-
ing the lowest memory address) gets transferred first. So 16-bit
data transfers require first transferring the least significant bits
7:0 and then transferring the most significant bits 15:8, where
bit 15 is the most significant bit in the word.
In addition, left channel data is always transferred before right
channel data with the AD1846. T he following figures should
make these requirements clear.
SAMPLE 6
MONO
MONO
MONO
MONO
SAMPLE 5
SAMPLE 4
SAMPLE 3
SAMPLE 2
SAMPLE 1
TIME
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Figure 7. 8-Bit Mono Data Stream Sequencing
SAMPLE 3
RIGHT
LEFT
RIGHT
LEFT
SAMPLE 3
SAMPLE 2
SAMPLE 2
SAMPLE 1
SAMPLE 1
TIME
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Figure 8. 8-Bit Stereo Data Stream Sequencing
TIME
MONO
MONO
SAMPLE 6
SAMPLE 5
SAMPLE 4
SAMPLE 3
SAMPLE 2
SAMPLE 1
BYTES 1 & 2
BYTES 3 & 4
Figure 9. 16-Bit Mono Data Stream Sequencing
TIME
RIGHT
LEFT
SAMPLE 3
SAMPLE 3
SAMPLE 2
SAMPLE 2
SAMPLE 1
SAMPLE 1
BYTES 1 & 2
BYTES 3 & 4
Figure 10. 16-Bit Stereo Data Stream Sequencing
Control and Programmed I/O (PIO) T ransfers
T his simpler mode of transfers is used both for control register
accesses and programmed I/O. T he 21 control and PIO data
registers cannot he accessed via DMA transfers. Playback PIO is
activated when both Playback Enable (PEN) is set and Playback
PIO (PPIO) is set. Capture PIO is activated when both Capture
Enable (CEN) is set and Capture PIO (CPIO) is set. See Fig-
ures 11 and 12 for the detailed timing of the control register/
PIO transfers. T he
RD
and
WR
signals are used to define the
actual read and write cycles, respectively. T he host holds
CS
LO during these transfers. T he DMA Capture Data Acknowl-
edge (
CDAK
) and Playback Data Acknowledge (
PDAK
) must
be held inactive, i.e., HI.
For read/capture cycles, the AD1846 will place data on the
DAT A7:0 lines while the host is asserting the read strobe,
RD
,
by holding it LO. For write/playback, the host must place data
on the DAT A7:0 pins while strobing the
WR
signal LO. T he
AD1846 latches the write/playback data on the rising edge of
the
WR
strobe.
When using PIO data transfers, the Status Register must be
polled to determine when data should be transferred. Note that
the ADC capture data will be ready (CRDY HI) from the previ-
ous sample period shortly before the DAC playback data is
ready (PRDY HI) for the next sample period. T he user should
not wait for both ADCs and DACs to become ready before initi-
ating data transfers. Instead, as soon as capture data is ready, it
should be read; as soon as the DACs are ready, playback data
should he written.
Values written to the X CT L1:0 bits in the Pin Control Register
(IA3:0 = 10) will be reflected in the state of the X CT L1:0 exter-
nal output pins. T his feature allows a simple method for signal-
ing or software control of external logic. Changes in state of the
external X CT L pins will occur within one sample period. Be-
cause their change is referenced to the internal sample clock, no
useful timing diagram can be constructed.
CDRQ /
PDRQ
OUTPUTS
CS INPUT
CDAK
INPUT
DATA7:0
OUTPUTS
RD INPUT
DBEN &
DBDIR
OUTPUTS
ADR1:0
INPUTS
t
DBDL
t
RDDV
t
ADSU
t
CSHD
t
CSSU
t
DHD1
t
ADHD
t
STW
t
SUDK2
t
SUDK1
Figure 11. Control Register/PIO Read Cycle
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1849KP | Serial-Port 16-Bit SoundPort Stereo Codec |
| AD1851 | 16-Bit, 16×Fs PCM Audio DACs(16位,單片PCM音頻D/A轉(zhuǎn)換器) |
| AD1892JR | Integrated Digital Receiver/Rate Converter |
| AD1892JRRL | Integrated Digital Receiver/Rate Converter |
| AD1892 | Integrated Digital Receiver/Rate Converter(數(shù)字音頻接收器/采樣率轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1846JP-REEL | 制造商:Analog Devices 功能描述: |
| AD1847 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundPort Stereo Codec |
| AD1847JP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1847JP-REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1847JST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundPort Stereo Codec |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。