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參數(shù)資料
| 型號： | AD1846JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 277K |
| 代理商： | AD1846JP |
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AD1846
REV. A
–12–
Direct Control Register Definitions
Index R egister (ADR 1:0 = 0)
AD R1:0
0
D ata 7
INIT
D ata 6
MCE
D ata 5
T RD
D ata 4
res
D ata 3
IX A3
D ata 2
IX A2
D ata 1
IX A1
D ata 0
IX A0
IX A3:0
Index Address. T hese bits define the address of the AD1846 register accessed by the Indexed Data Register. T hese bits
are read/write.
Reserved for future expansion. Always write a zero to this bit.
T ransfer Request Disable. T his bit, when set, causes all data transfers to cease when the Interrupt Status (INT ) bit of the
Status Register is set.
0
T ransfers Enabled During Interrupt. PDRQ and CDRQ pin outputs are generated uninhibited by interrupts.
DMA Current Counter Register decrements with every sample period when either PEN or CEN are enabled.
1
T ransfers Disabled By Interrupt. PDRQ and CDRQ pin outputs are generated only if INT bit is 0 (when either
PEN or CEN, respectively, are enabled). Any pending playback or capture requests are allowed to complete at the
time when T RD is set. After pending requests complete, midscale inputs will be internally generated for the
DACs, and the ADC output buffer will contain the last valid output. Clearing the sticky INT bit (or the T RD bit)
will cause the resumption of playback and/or capture requests (presuming PEN and/or CEN are enabled). T he
DMA Current Counter Register will not decrement while both the T RD bit is set and the INT bit is a one.
Mode Change Enable. T his bit must be set whenever the current functional mode of the AD1846 is changed. Specifically,
the Clock and Data Format and Interface Configuration registers cannot be changed unless this bit is set. T he exceptions
are CEN and PEN in the Interface Configuration which can be changed “on-the-fly.” MCE should be cleared at the com-
pletion of the desired register changes. T he DAC outputs are automatically muted when the MCE bit is set. After MCE is
cleared, the DAC outputs will be restored to the state specified by the LDM and RDM mute bits.
Both ADCs and DACs are automatically muted for approximately 128 sample cycles after exiting the MCE state to allow
the reference and all filters to settle. T he ADCs will produce midscale values; the DACs’ analog output will be muted. All
converters are internally operating during these
≈
128 sample cycles, and the AD1846 will expect playback data and will
generate (midscale) capture data. Note that the autocalibrate-in-process (ACI) bit will be set on exit from the MCE state
regardless of whether or not ACAL was set. ACI will remain HI for these
≈
128 sample cycles; system software should poll
this bit rather than count cycles.
Special sequences must be followed if autocalibrate (ACAL) is set or sample rates are changed (CFS2:0 and or CSS)
during mode change enable. See the “Autocalibration” and “Changing Sample Rates” sections below.
AD1846 Initialization. T his bit is set when the AD1846 is in a state which cannot respond to parallel bus cycles. T his bit
is read only.
Immediately after reset and once the AD1846 has left the INIT state, the initial value of this register will be “0100 0000 (40h).”
During AD1846 initialization, this register cannot be written to and will always read “100x 0000 (80h).”
res
T RD
MCE
INIT
Indexed Data R egister (ADR 1:0 = 1)
AD R1:0
D ata 7
1
IX D 7
D ata 6
IX D 6
D ata 5
IX D 5
D ata 4
IX D 4
D ata 3
IX D 3
D ata 2
IX D 2
D ata 1
IX D 1
D ata 0
IX D 0
IX D7:0
Indexed Register Data. T hese bits contain the contents of the AD1846 register referenced by the Indexed Data Register.
During AD1846 initialization, this register cannot be written to and will always read as “1000 0000 (80h).”
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD1846JP-REEL | 制造商:Analog Devices 功能描述: |
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