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參數(shù)資料
| 型號： | AD10465BZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 14BIT 68-CLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 3.9W |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-CLCC |
| 供應(yīng)商設(shè)備封裝： | 68-CLCC（24.13x24.13） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 6 個單端，雙極 |
AD10465
Rev. A | Page 13 of 24
APPLYING THE AD10465
ENCODING THE AD10465
JITTER CONSIDERATIONS
The AD10465 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Maintaining 14-bit accuracy places a premium on encode clock
phase noise. SNR performance can easily degrade by 3 dB to
4 dB with 32 MHz input signals when using a high jitter clock
source. See the Analog Devices Application Note AN-501, Aper-
ture Uncertainty and ADC System Performance, for complete
details. For optimum performance, the AD10465 must be
clocked differentially. The encode signal is usually ac-coupled
into the ENCODE and
The signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, Equation 1 accurately
predicts the SNR based on three terms. These are jitter, average
DNL error, and thermal noise. Each of these terms contributes
to the noise within the converter.
()
2
/
1
2
1
log
20
+
×
+
+
×
=
n
rms
NOISE
j
ANALOG
N
v
rms
t
f
SNR
π
ε
(1)
ENCODE pins via a transformer or
capacitors. These pins are biased internally and require no
additional bias.
Figure 20 shows one preferred method for clocking the
AD10465. The clock source (low jitter) is converted from
single-ended to differential using an RF transformer. The back-
to-back Schottky diodes across the transformer secondary limit
clock excursions into the AD10465 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to the other portions of the
AD10465, and limits the noise presented to the ENCODE
inputs. A crystal clock oscillator can also be used to drive the
RF transformer if an appropriate limiting resistor (typically
100 Ω) is placed in the series with the primary.
where:
fANALOG is the analog input frequency.
tj rms is the rms jitter of the encode (rms sum of encode source
and internal encode circuitry).
ε is the average DNL of the ADC (typically 0.50 LSB).
N is the number of bits in the ADC.
VNOISE rms is the V rms noise referred to the analog input of the
ADC (typically 5 LSB).
02
35
6-
0
20
T1-4T
0.1nF
ENCODE
AD10465
HSMS2812
DIODES
CLOCK
SOURCE
100
For a 14-bit analog-to-digital converter like the AD10465,
aperture jitter can greatly affect the SNR performance as the
analog frequency is increased. The chart below shows a family
of curves that demonstrates the expected SNR performance of
the AD10465 as jitter increases. The chart is derived from
Figure 20. Crystal Clock Oscillator, Differential ENCODE
If a low jitter ECL/PECL clock is available, another option is to
ac couple a differential ECL/PECL signal to the ENCODE and
For a complete discussion of aperture jitter, please consult the
Analog Devices Application Note AN-501, Aperture Uncertainty
and ADC System Performance.
ENCODE input pins as shown in Figure 21. A device that offers
excellent jitter performance is the MC100LVEL16 (or same
family) from Motorola.
71
70
69
68
67
66
65
64
63
62
61
60
3.
9
0.
1
0.
3
0.
5
0.
7
0.
9
1.
1
1.
3
1.
5
1.
7
1.
9
2.
1
2.
3
2.
5
2.
7
2.
9
3.
1
3.
3
3.
5
3.
7
S
NR
(
d
B
F
S
)
RMS CLOCK JITTER (ps)
02
35
6-
0
22
AIN = 5MHz
AIN = 10MHz
AIN = 20MHz
AIN = 32MHz
02
35
6-
0
21
ENCODE
AD10465
0.1F
ECL/
PECL
VT
Figure 21. Differential ECL for ENCODE
Figure 22. SNR vs. Jitter
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