1 See Table 3. 2 Gain tests are p" />
參數(shù)資料
型號(hào)： AD10465BZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 20/24頁(yè)
文件大小： 0K
描述： IC ADC DUAL 14BIT 68-CLCC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 3.9W
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 68-CLCC
供應(yīng)商設(shè)備封裝： 68-CLCC（24.13x24.13）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 6 個(gè)單端，雙極
AD10465
Rev. A | Page 5 of 24
2 Gain tests are performed on AIN1 input voltage range.
3 Input capacitance specification combines AD8037 die capacitance and ceramic package capacitance.
4 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
5 All ac specifications tested by driving ENCODE and ENCODE differentially.
6 Minimum and maximum conversion rates allow for variation in encode duty cycle of 50% ± 5%.
7 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). ENCODE = 65 MSPS. SNR is
reported in dBFS, related back to converter full power.
8 Analog input signal power at –1 dBFS. Signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. ENCODE = 65 MSPS.
9 Analog input signal power swept from 1 dBFS to 60 dBFS; SFDR is the ratio of converter full scale to worst spur.
10 Both input tones at 7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermodulation product.
11 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.
12 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF degrade performance.
13 Supply voltage recommended operating range. AVCC can be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AVCC = 5.0 V to 5.25 V.
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