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參數(shù)資料
| 型號： | A3PN125-2VQ100 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 3072 CLBS, 125000 GATES, PQFP100 |
| 封裝： | 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, VQFP-100 |
| 文件頁數(shù)： | 72/106頁 |
| 文件大?。?/td> | 3324K |
| 代理商： | A3PN125-2VQ100 |
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ProASIC3 nano DC and Switching Characteristics
2- 54
R e visio n 8
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-57. Table 2-67 to Table 2-72 on page 2-56 present
minimum and maximum global clock delays within each device. Minimum and maximum delays are
measured with minimum and maximum loading.
Timing Characteristics
Table 2-67 A3PN010 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter Description
–2
–1
Std.
Units
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2
tRCKL
Input LOW Delay for Global Clock
0.60
0.79
0.69
0.90
0.81
1.06
ns
tRCKH
Input HIGH Delay for Global Clock
0.62
0.84
0.70
0.96
0.82
1.12
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.22
0.26
0.30
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-68 A3PN015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter Description
–2
–1
Std.
Units
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2
tRCKL
Input LOW Delay for Global Clock
0.66
0.91
0.75
1.04
0.89
1.22
ns
tRCKH
Input HIGH Delay for Global Clock
0.67
0.96
0.77
1.10
0.90
1.29
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.29
0.33
0.39
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3PN125-2VQ100I | 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14） |
| A3PN125-2VQG100 | 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14） |
| A3PN125-2VQG100I | 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14） |
| A3PN125-DIELOT | 制造商:Microsemi Corporation 功能描述:A3PN125-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film |
| A3PN125-VQ100 | 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14） |
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