參數(shù)資料
型號(hào)： A3PN125-2VQ100
元件分類： FPGA
英文描述： FPGA, 3072 CLBS, 125000 GATES, PQFP100
封裝： 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, VQFP-100
文件頁(yè)數(shù)： 16/106頁(yè)
文件大?。?/td> 3324K
代理商： A3PN125-2VQ100
ProASIC3 nano Flash FPGAs
R e visio n 8
2 -3
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up
behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4
for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±
0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the
"Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 nano Device Family
User’s Guide for information on clock and lock recovery.
Table 2-4 Overshoot and Undershoot Limits 1
VCCI and VMV
Average VCCI–GND Overshoot or Undershoot
Duration as a Percentage of Clock Cycle 2
Maximum Overshoot/
Undershoot 2
2.7 V or less
10%
1.4 V
5%
1.49 V
3 V
10%
1.1 V
5%
1.19 V
3.3 V
10%
0.79 V
5%
0.88 V
3.6 V
10%
0.45 V
5%
0.54 V
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
相關(guān)PDF資料
PDF描述
A3PN125-2VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-2VQG100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQ100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQ100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PN125-2VQ100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PN125-2VQG100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PN125-2VQG100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PN125-DIELOT 制造商:Microsemi Corporation 功能描述:A3PN125-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film
A3PN125-VQ100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
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