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參數(shù)資料
| 型號： | A1440A-VQG100I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 89/90頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 4K GATES 100-VQFP |
| 產(chǎn)品變化通告： | A1440A Family Discontinuation 24/Jan/2012 |
| 標準包裝： | 90 |
| 系列： | ACT™ 3 |
| LAB/CLB數(shù)： | 564 |
| 輸入/輸出數(shù)： | 83 |
| 門數(shù)： | 4000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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R e visio n 3
2 -1
2 – Detailed Specifications
This section of the datasheet is meant to familiarize the user with the architecture of the ACT 3 family of
FPGA devices. A generic description of the family will be presented first, followed by a detailed
description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The
on-chip circuitry required to program the devices is not covered.
Topology
The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad
Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is
similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array
itself consists of alternating rows of modules and channels. The logic modules and channels are in the
center of the array; the I/O modules are located along the array periphery. A simplified floor plan is
depicted in Figure 2-1.
Figure 2-1
Generalized Floor Plan of ACT 3 Device
IO
C
SC
S
IO
C
SC
S
IO
C
SC
S
IO
C
BIO IO
IO
BIN S
C
S
IO
BIN S
C
S
IO
BIN S
C
S
IO
CLKM
IO
BIN S
C
IO
CS
SC
S
IO
C
An Array with
n rows and m columns
Top I/Os
Bottom I/Os
Left I/Os
Right I/Os
Rows
n+1
n
n–1
2
1
0
Channels
n+1
n
n–1
2
1
0
n+2
0
1
2
3
4
5
c–1
c
c+1
m m+1 m+2 m+3
Columns
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