Table 2-25 A1425A, A" />
參數(shù)資料
型號(hào)： A1440A-VQG100I
廠商： Microsemi SoC
文件頁數(shù)： 31/90頁
文件大?。?/td> 0K
描述： IC FPGA 4K GATES 100-VQFP
產(chǎn)品變化通告： A1440A Family Discontinuation 24/Jan/2012
標(biāo)準(zhǔn)包裝： 90
系列： ACT™ 3
LAB/CLB數(shù)： 564
輸入/輸出數(shù)： 83
門數(shù)： 4000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 - 29
A1425A, A14V25A Timing Characteristics (continued)
Table 2-25 A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Dedicated (hardwired) I/O Clock Network
–3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units
Parameter/Description
Min. Max. Min. Max. Min. Max. Min. Max. Min.
Max.
tIOCKH
Input Low to High (pad to I/O module
input)
2.0
2.3
2.6
3.0
3.5
ns
tIOPWH
Minimum Pulse Width High
1.9
2.4
3.3
3.8
4.8
ns
tIPOWL
Minimum Pulse Width Low
1.9
2.4
3.3
3.8
4.8
ns
tIOSAPW Minimum Asynchronous Pulse Width
1.9
2.4
3.3
3.8
4.8
ns
tIOCKSW Maximum Skew
0.4
ns
tIOP
Minimum Period
4.0
5.0
6.8
8.0
10.0
ns
fIOMAX
Maximum Frequency
250
200
150
125
100
MHz
Dedicated (hardwired) Array Clock
tHCKH
Input Low to High (pad to S-module
input)
3.0
3.4
3.9
4.5
5.5
ns
tHCKL
Input High to Low (pad to S-module
input)
3.0
3.4
3.9
4.5
5.5
ns
tHPWH
Minimum Pulse Width High
1.9
2.4
3.3
3.8
4.8
ns
tHPWL
Minimum Pulse Width Low
1.9
2.4
3.3
3.8
4.8
ns
tHCKSW
Delta High to Low, Low Slew
0.3
ns
tHP
Minimum Period
4.0
5.0
6.8
8.0
10.0
ns
fHMAX
Maximum Frequency
250
200
150
125
100
MHz
Routed Array Clock Networks
tRCKH
Input Low to High (FO = 64)
3.7
4.1
4.7
5.5
9.0
ns
tRCKL
Input High to Low (FO = 64)
4.0
4.5
5.1
6.0
9.0
ns
tRPWH
Min. Pulse Width High (FO = 64)
3.3
3.8
4.2
4.9
6.5
ns
tRPWL
Min. Pulse Width Low (FO = 64)
3.3
3.8
4.2
4.9
6.5
ns
tRCKSW
Maximum Skew (FO = 128)
0.7
0.8
0.9
1.0
ns
tRP
Minimum Period (FO = 64)
6.8
8.0
8.7
10.0
13.4
ns
fRMAX
Maximum Frequency (FO = 64)
150
125
115
100
75
MHz
Clock-to-Clock Skews
tIOHCKSW I/O Clock to H-Clock Skew
0.0
1.7
0.0
1.8
0.0
2.0
0.0
2.2
0.0
3.0
ns
tIORCKSW I/O Clock to R-Clock Skew (FO = 64)
(FO = 80)
0.0
1.0
3.0
0.0
1.0
3.0
0.0
1.0
3.0
0.0
1.0
3.0
0.0
3.0
ns
tHRCKSW H-Clock to R-Clock Skew (FO = 64)
(FO = 80)
0.0
1.0
3.0
0.0
1.0
3.0
0.0
1.0
3.0
0.0
1.0
3.0
0.0
1.0
3.0
ns
Notes:
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at
2. Delays based on 35 pF loading.
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