參數(shù)資料
型號(hào)： A1440A-VQG100I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 14/90頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 4K GATES 100-VQFP
產(chǎn)品變化通告： A1440A Family Discontinuation 24/Jan/2012
標(biāo)準(zhǔn)包裝： 90
系列： ACT™ 3
LAB/CLB數(shù)： 564
輸入/輸出數(shù)： 83
門(mén)數(shù)： 4000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 - 13
Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for
each circuit component of interest. Measurements have been made over a range of frequencies at a
fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used
over a wide range of operating conditions. Equivalent capacitance values are shown in Figure 2-10.
To calculate the active power dissipated from the complete design, the switching frequency of each part
of the logic must be known. EQ 5 shows a piece-wise linear summation over all components.
Power =VCC2 * [(m * CEQM * fm)modules + (n * CEQI * fn) inputs
+ (p * (CEQO+ CL) * fp)outputs
+ 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1
+ 0.5 * (q2 * CEQCR * fq2)routed_Clk2
+ (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk
+ (s2 * CEQCI * fs2)IO_Clk]
EQ 5
Where:
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
q1 = Number of clock loads on the first routed array clock
q2 = Number of clock loads on the second routed array clock
r1 = Fixed capacitance due to first routed array clock
r2 = Fixed capacitance due to second routed array clock
s1 = Fixed number of clock loads on the dedicated array clock
s2 = Fixed number of clock loads on the dedicated I/O clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
CEQCD = Equivalent capacitance of dedicated array clock in pF
CEQCI = Equivalent capacitance of dedicated I/O clock in pF
CL = Output lead capacitance in pF
fm = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
fq2 = Average second routed array clock rate in MHz
fs1 = Average dedicated array clock rate in MHz
fs2 = Average dedicated I/O clock rate in MHz
Table 2-10 CEQ Values for Microsemi FPGAs
Item
CEQ Value
Modules (CEQM)
6.7
Input Buffers (CEQI)7.2
Output Buffers (CEQO)
10.4
Routed Array Clock Buffer Loads (CEQCR)
1.6
Dedicated Clock Buffer Loads (CEQCD)
0.7
I/O Clock Buffer Loads (CEQCI)
0.9
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