參數(shù)資料
型號： 9S12B128DGV1
英文描述： 9S12B128 Device Guide
中文描述： 9S12B128設備指南
文件頁數(shù)： 67/128頁
文件大小： 1823K
代理商： 9S12B128DGV1
Device User Guide —9S12B128DGV1/D V01.11
67
Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1
lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
Vector Address
Interrupt Source
CCR
Mask
Local Enable
HPRIO Value
to Elevate
$FFFE, $FFFF
External Reset, Power On Reset or Low
Voltage Reset (see CRG Flags Register
to determine reset source)
Clock Monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real Time Interrupt
Standard Timer channel 0
Standard Timer channel 1
Standard Timer channel 2
Standard Timer channel 3
Standard Timer channel 4
Standard Timer channel 5
Standard Timer channel 6
Standard Timer channel 7
Standard Timer overflow
Pulse accumulator A overflow
Pulse accumulator input edge
SPI0
None
None
–
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
PLLCTL (CME, SCME)
COP rate select
None
None
None
IRQCR (IRQEN)
CRGINT (RTIE)
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TMSK2 (TOI)
PACTL (PAOVI)
PACTL (PAI)
SPICR1 (SPIE, SPTIE)
SCICR2
(TIE, TCIE, RIE, ILIE)
SCICR2
(TIE, TCIE, RIE, ILIE)
ATDCTL2 (ASCIE)
Reserved
PIEJ
(PIEJ7, PIEJ6, PIEJ1, PIEJ0)
–
–
–
–
–
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$FFD6, $FFD7
SCI0
I-Bit
$D6
$FFD4, $FFD5
SCI1
I-Bit
$D4
$FFD2, $FFD3
$FFD0, $FFD1
ATD
I-Bit
I-Bit
$D2
$D0
Reserved
$FFCE, $FFCF
Port J
I-Bit
$CE
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