參數資料
型號： 9S12B128DGV1
英文描述： 9S12B128 Device Guide
中文描述： 9S12B128設備指南
文件頁數： 41/128頁
文件大小： 1823K
代理商： 9S12B128DGV1
Device User Guide —9S12B128DGV1/D V01.11
41
$016C
CAN0RDLR
Read:
Write:
Read:
Write:
Read:
Write:
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Write:
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Write:
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Write:
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DLC3
DLC2
DLC1
DLC0
$016D
Reserved
$016E
CAN0RTSRH
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
$016F
CAN0RTSRL
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
$0170
Extended ID
CAN0TIDR0
Standard ID
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
$0171
Extended ID
CAN0TIDR1
Standard ID
ID20
ID19
ID18
SRR=1
IDE=1
ID17
ID16
ID15
ID2
ID1
ID0
RTR
IDE=0
$0172
Extended ID
CAN0TIDR2
Standard ID
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
$0173
Extended ID
CAN0TIDR3
Standard ID
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$0174-
$017B
CAN0TDSR0 -
CAN0TDSR7
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$017C
CAN0TDLR
DLC3
DLC2
DLC1
DLC0
$017D
CAN0TTBPR
PRIO7
PRIO6
PRIO5
PRIO4
PRIO3
PRIO2
PRIO1
PRIO0
$017E
CAN0TTSRH
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
$017F
CAN0TTSRL
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
$0180 - $01FF
Reserved
Address
$0180 -
$01FF
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved
Read:
Write:
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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