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| 型號(hào)： | 9S12B128DGV1 |
| 英文描述： | 9S12B128 Device Guide |
| 中文描述： | 9S12B128設(shè)備指南 |
| 文件頁(yè)數(shù)： | 105/128頁(yè) |
| 文件大?。?/td> | 1823K |
| 代理商： | 9S12B128DGV1 |
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Device User Guide —9S12B128DGV1/D V01.11
105
A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-19
summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-19 Startup Characteristics
A.5.1.1 POR
ThereleaselevelV
PORD
(see
Table A-17
)andtheassertlevelV
PORA
(see
Table A-17
)arederivedfrom
the V
DD
Supply. They are also valid if the device is powered externally. After releasing the POR reset the
oscillator and the clock quality check are started. If after a time t
CQOUT
no valid oscillation is detected, the
MCU will start using the internal self clock. The fastest startup time possible is given by n
uposc
.
A.5.1.2 LVR
The assert level V
LVRA
(see
Table A-17
) is derived from the V
DD
Supply. After releasing the LVR reset
the oscillator and the clock quality check are started. If after a time t
CQOUT
no valid oscillation is detected,
the MCU will start using the internal self clock. The fastest startup time possible is given by n
uposc
.
A.5.1.3 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
codewhenVDD5isoutofspecificationlimits,theSRAMcontentsintegrityisguaranteedifafterthereset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.4 External Reset
When external reset is asserted for a time greater than PW
RSTL
the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
Conditions are shown in
Table A-4
unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
D Reset input pulse width, minimum input time
PW
RSTL
2
t
osc
2
D Startup from Reset
n
RST
192
196
n
osc
3
D Interrupt pulse width, IRQ edge-sensitive mode
PW
IRQ
20
ns
4
D Wait recovery startup time
t
WRS
14
t
cyc
5
T Voltage Regulator Return from Pseudo Stop
t
vup
100
μ
s
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