參數(shù)資料
型號： 950812YGT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
文件頁數(shù)： 28/30頁
文件大?。?/td> 227K
代理商： 950812YGT
IDTTM Frequency Generator with 200MHz Differential CPU Clocks
0542J—01/25/10
ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
7
FS5FS4 FS3FS1 FS0
Freq
Center
Down
11
12
13
14
11
12
13
14
0
0000
66.66
Center
0.40%
8D
9B
02
18
10001101 10011011 00000010 00011000
1
0
0001
99.99
Center
0.40%
8D
9B
02
18
10001101 10011011 00000010 00011000
2
0
0010
199.98
Center
0.40%
8D
9B
02
18
10001101 10011011 00000010 00011000
3
0
0011
133.32
Center
0.40%
8D
9B
02
18
10001101 10011011 00000010 00011000
4
0
0100
66.50
Down
-0.48%
8D
9A
EF
17
10001101 10011010 11101111 00010111
5
0
0101
99.75
Down
-0.48%
8D
9A
EF
17
10001101 10011010 11101111 00010111
6
0
0110
199.50
Down
-0.48%
8D
9A
EF
17
10001101 10011010 11101111 00010111
7
0
0111
133.00
Down
-0.48%
8D
9A
EF
17
10001101 10011010 11101111 00010111
8
0
1000
66.34
Down
-0.98%
8D
99
E7
17
10001101 10011001 11100111 00010111
9
0
1001
99.51
Down
-0.98%
8D
99
E7
17
10001101 10011001 11100111 00010111
10
0
1010
199.02
Down
-0.98%
8D
99
E7
17
10001101 10011001 11100111 00010111
11
0
1011
132.68
Down
-0.98%
8D
99
E7
17
10001101 10011001 11100111 00010111
12
0
1100
66.16
Down
-1.52%
90
EB
DD
17
10010000 11101011 11011101 00010111
13
0
1101
99.23
Down
-1.52%
90
EB
DD
17
10010000 11101011 11011101 00010111
14
0
1110
198.47
Down
-1.52%
90
EB
DD
17
10010000 11101011 11011101 00010111
15
0
1111
132.31
Down
-1.52%
90
EB
DD
17
10010000 11101011 11011101 00010111
16
1
0000
66.66
Center
0.51%
8D
9B
05
18
10001101 10011011 00000101 00011000
17
1
0001
99.99
Center
0.51%
8D
9B
05
18
10001101 10011011 00000101 00011000
18
1
0010
199.98
Center
0.51%
8D
9B
05
18
10001101 10011011 00000101 00011000
19
1
0011
133.32
Center
0.51%
8D
9B
05
18
10001101 10011011 00000101 00011000
20
1
0100
66.66
Center
0.74%
8D
9B
0B
18
10001101 10011011 00001011 00011000
21
1
0101
99.99
Center
0.74%
8D
9B
0B
18
10001101 10011011 00001011 00011000
22
1
0110
199.98
Center
0.74%
8D
9B
0B
18
10001101 10011011 00001011 00011000
23
1
0111
133.32
Center
0.74%
8D
9B
0B
18
10001101 10011011 00001011 00011000
24
1
1000
70.00
Center
0.35%
8D
B0
35
19
10001101 10110000 00110101 00011001
25
1
1001
105.00
Center
0.35%
8D
B0
35
19
10001101 10110000 00110101 00011001
26
1
1010
210.00
Center
0.35%
8D
B0
35
19
10001101 10110000 00110101 00011001
27
1
1011
140.00
Center
0.35%
8D
B0
35
19
10001101 10110000 00110101 00011001
28
1
1100
73.33
Center
0.34%
89
4A
68
1A
10001001 01001010 01101000 00011010
29
1
1101
109.99
Center
0.34%
89
4A
68
1A
10001001 01001010 01101000 00011010
30
1
1110
219.98
Center
0.34%
89
4A
68
1A
10001001 01001010 01101000 00011010
31
1
1111
146.65
Center
0.34%
89
4A
68
1A
10001001 01001010 01101000 00011010
I2C read back values in Hex.
Bytes
I2C read back values in binary.
Spread
CPU
ADDRESS
Table 8: Byte 11-14 Defaults
Table 7
3V66 (0:1) I
2C Control Table
Note: Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 33 and 35.
CPU_STOP#
(Pin 53)
Byte 5
Bit 4
3V66 (1:0)
0
Running
1
Running
0
1
Stopped
1
0
Running
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