參數(shù)資料
型號： 950812YGT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
文件頁數(shù)： 25/30頁
文件大?。?/td> 227K
代理商： 950812YGT
IDTTM Frequency Generator with 200MHz Differential CPU Clocks
0542J—01/25/10
ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
4
Frequency Select Table 2
Frequency Select Table 1
66MHz_OU
T (2:0)
66MHz_IN
FS
2
FS
1
FS
0
3V66 (4:2)
3V66 _5
0
66.66
33.33
14.318
48.008
0
1
100.00
66.66
33.33
14.318
48.008
0
1
0
200.00
66.66
33.33
14.318
48.008
0
1
133.33
66.66
33.33
14.318
48.008
1
0
66.66
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
1
0
1
100.00
66.66
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
1
0
200.00
66.66
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
1
133.33
66.66
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
0
70.00
35.00
14.318
48.008
0
1
105.00
70.00
35.00
14.318
48.008
0
1
0
Tristate
0
1
140.00
70.00
35.00
14.318
48.008
1
0
70.00
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
1
0
1
105.00
70.00
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
1
0
Tristate
1
140.00
70.00
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
5% Overclocking
0
73.32
36.66
14.318
48.008
0
1
110.00
73.32
36.66
14.318
48.008
0
1
0
Test/2
Test/4
Test/8
Test
Test/2
Test
0
1
146.60
73.32
36.66
14.318
48.008
1
0
73.32
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
1
0
1
110.00
73.32
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
1
0
Test/2
Test/4
Test/8
Test
Test/2
Test
1
146.60
73.32
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
10% Overclocking
Standard Clocking
5% Overclocking
110
(See table 2)
111
(See table 2)
REF MHz
USB/DOT
MHz
Clocking Mode
Freq Sel
CPU MHz
3V66 MHz
FS(5:3)
PCI MHz
From
000
to
101
(See table 2)
FS
5
FS
4
FS
3
000
001
010
011
100
101
110
111
+/-0.35%, Center Spread
0 to -1.5%, Down Spread
+/-0.5%, Center Spread
+/-0.75%, Center Spread
+/-0.35%, Center Spread
10% Overclocking
Clocking Mode
No Spread (default)
or +/-0.4%
0 to -0.5%, Down Spread
0 to -1.0%, Down Spread
Standard Clocking
CPU, 3V66, 66MHz_OUT,
66MHz_IN, PCI
5% Overclocking
Freq Sel
Standard Clocking
Note: To enable spread, Byte 0 Bit 7 must be set to 1.
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