參數(shù)資料
型號： 950812YGT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
文件頁數(shù)： 20/30頁
文件大?。?/td> 227K
代理商： 950812YGT
IDTTM Frequency Generator with 200MHz Differential CPU Clocks
0542J—01/25/10
ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
27
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping
of the power supply until the time that stable clocks are output from the clock chip. If the I
2C Bit 6 of Byte 0 is programmed to
"1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagrams
CPU 1.0V Configuration test load board termination
TLA
TLB
RREF=221 Ohms
1%
MULTSEL Pin must be Low
Rs=33 Ohms
1%
Rs=33 Ohms
1%
Rp=63.4 Ohms
1%
Rp=63.4 Ohms
1%
Rdif=475 Ohms
1%
2pF
5%
2pF
5%
CPUCLKT test
point
CPUCLKC test
point
CLK408
CPU 0.7V Configuration test load board termination
TLA
TLB
MULTSEL Pin must be High
Rs=33 Ohms
5%
Rs=33 Ohms
5%
Rp=49.9 Ohms
1%
Rp=49.9 Ohms
1%
Rset=475 Ohms
1%
2pF
5%
2pF
5%
CPUCLKT test
point
CPUCLKC test
point
CLK408
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