參數(shù)資料
型號(hào)： 950812YGT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
文件頁(yè)數(shù)： 19/30頁(yè)
文件大小： 227K
代理商： 950812YGT
IDTTM Frequency Generator with 200MHz Differential CPU Clocks
0542J—01/25/10
ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
26
PD# Functionality
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CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
De-assertion of CPU_STOP# Waveforms
All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the de-
assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of Byte
1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# de-assertion.
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be
held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both CPU and
CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and description is
applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one
clock cycle to complete.
PD# - Assertion (transition from logic "1" to logic "0")
Power Down Assertion of Waveforms
0ns
PD#
CPUCLKT 100MHz
CPUCLKC 100MHz
3V66MHz
66MHz_IN
66MHz_OUT
PCICLK 33MHz
USB 48MHz
REF 14.318MHz
25ns
50ns
CPU_STOP#
CPUCLKT(2:0)
*CPUCLKT(2:0)TS
CPUCLKC(2:0)
Tdrive_CPU_STOP# <10ns @ 200mV
*Signal TS is CPUCLKT in Tri-State mode
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