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參數(shù)資料
| 型號： | 935270057557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 9/52頁 |
| 文件大?。?/td> | 680K |
| 代理商： | 935270057557 |
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Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 02 — 14 March 2003
17 of 49
9397 750 11192
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.6.2
Block DMA transfers (DMA mode 1)
Figure 11 shows TXRDY and RXRDY in DMA mode 1.
Transmitter: TXRDY is active when there is a trigger level number of spaces
available. It becomes inactive when the FIFO is full.
Receiver: RXRDY becomes active when the trigger level has been reached, or when
a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in
the RX FIFO is agged by LSR[7].
6.7 Sleep mode
Sleep mode is an enhanced feature of the SC16C754 UART. It is enabled when
EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is
entered when:
The serial data input line, RX, is idle (see Section 6.8 “Break and time-out
The TX FIFO and TX shift register are empty.
There are no interrupts pending except THR and time-out interrupts.
Remark: Sleep mode will not be entered if there is data in the RX FIFO.
In sleep mode, the UART clock and baud rate clock are stopped. Since most registers
are clocked using these clocks, the power consumption is greatly reduced. The UART
will wake up when any change is detected on the RX line, when there is any change
in the state of the modem input pins, or if data is written to the TX FIFO.
Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not
be done during sleep mode. Therefore, it is advisable to disable sleep mode using
IER[4] before writing to DLL or DLH.
Fig 11. TXRDY and RXRDY in DMA mode 1.
TX
wrptr
TXRDY
FIFO FULL
TXRDY
RX
rdptr
FIFO EMPTY
RXRDY
AT LEAST ONE
LOCATION FILLED
RXRDY
002aaa234
TRIGGER
LEVEL
TRIGGER
LEVEL
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