參數(shù)資料
型號(hào)： 935270057557
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù)： 20/52頁
文件大?。?/td> 680K
代理商： 935270057557
Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 02 — 14 March 2003
27 of 49
9397 750 11192
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.7 Modem status register (MSR)
This 8-bit register provides information about the current state of the control lines
from the mode, data set, or peripheral device to the processor. It also indicates when
a control input from the modem changes state. Table 15 shows modem status
register bit settings per channel.
[1]
The primary inputs RI, CD, CTS, DSR are all Active-LOW, but their registered equivalents in the MSR
and MCR (in loop-back) registers are Active-HIGH.
7.8 Interrupt enable register (IER)
The interrupt enable register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from
LOW to HIGH. The INT output signal is activated in response to interrupt generation.
Table 16 shows interrupt enable register bit settings.
Table 15:
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD (Active-HIGH, logical 1). This bit is the complement of the CD input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[3].
6
MSR[6]
RI (Active-HIGH, logical 1). This bit is the complement of the RI input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[2].
5
MSR[5]
DSR (Active-HIGH, logical 1). This bit is the complement of the DSR
input during normal mode. During internal loop-back mode, it is
equivalent MCR[0].
4
MSR[4]
CTS (Active-HIGH, logical 1). This bit is the complement of the CTS
input during normal mode. During internal loop-back mode, it is
equivalent to MCR[1].
3
MSR[3]
CD. Indicates that CD input (or MCR[3] in loop-back mode) has
changed state. Cleared on a read.
2
MSR[2]
RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed
state from LOW to HIGH. Cleared on a read.
1
MSR[1]
DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has
changed state. Cleared on a read.
0
MSR[0]
CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has
changed state. Cleared on a read.
Table 16:
Interrupt Enable Register bits description
Bit
Symbol
Description
7
IER[7] [1]
CTS interrupt enable.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt.
6
IER[6] [1]
RTS interrupt enable.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt.
5
IER[5] [1]
Xoff interrupt.
Logic 0 = Disable the Xoff interrupt (normal default condition).
Logic 1 = Enable the Xoff interrupt.
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