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參數(shù)資料
| 型號： | 935268625518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 63/82頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625518 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
66 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
Tcy1 is the total cycle time, consisting of the command active time tw1 and is the command recovery
(= inactive) time tw2: Tcy1 =tw1 +tw2. The minimum timing requirements for Tcy1, tw1 and tw2 must all
be met. Since Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host implementation must
lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the
IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
14.3.4
UDMA mode
tsu2(min)
data set-up time before DIOR/DIOW off
(minimum)
100
30
20
ns
th2(min)
data hold time after DIOW off (minimum)
20
15
10
ns
tsu1(min)
DACK set-up time before DIOR/DIOW on
(minimum)
000ns
th1(min)
DACK hold time after DIOR/DIOW off
(minimum)
20
55ns
tw2(min)
DIOR recovery time (minimum)[1]
50
25
ns
DIOW recovery time (minimum)[1]
215
50
25
ns
td2(max)
DIOR on to DREQ off delay (maximum)
120
40
35
ns
DIOW on to DREQ off delay (maximum)
40
35
ns
td3(max)
DACK off to data lines three-state delay
(maximum)
20
25
ns
Table 80:
MDMA mode timing parameters…continued
VCC = 4.0 to 5.5 V; VGND =0V; Tamb = 40 to +85 °C.
Symbol
Parameter
Mode 0
Mode 1
Mode 2
Unit
(1) DATA[15:0] and strobe signals at the receiver require some time to stabilize due to the settling time and propagation delay
of the cable.
Fig 28. UDMA timing: sustained synchronous burst.
DATA [15:0] (1) (sender)
DIOR (1) (sender)
DATA [15:0] (1) (receiver)
IORDY (1) (receiver)
tsu1
th1
th2
tsu2
th1
Tcy1
MGT507
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