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參數(shù)資料
| 型號： | 935268625518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 56/82頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625518 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
6 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
DIOR
14
I/O
DMA read strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see Table 35 and
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
DIOW
15
I/O
DMA write strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see Table 35 and
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
INTRQ
16
I
interrupt request input from ATA/ATAPI peripheral
input pad; TTL with hysteresis; 5 V tolerant; internal
pull-down resistor.
CS1[5]
17
O
chip select output for ATA/ATAPI device; see Table 33 and
CMOS output; 5 ns slew rate control
CS0[5]
18
O
chip select output for ATA/ATAPI device; see Table 33 and
CMOS output; 5 ns slew rate control
BUS_CONF/
DA0[5]
19
I/O
during power-up: input to select the bus conguration;
0 — Split Bus mode; multiplexed 8-bit address/data bus on
AD[7:0], separate DMA data bus on DATA[15:0][4]
1 — Generic Processor mode; separate 8-bit address on
AD[7:0], 16-bit processor data bus on DATA[15:0]. DMA is
multiplexed on the processor bus as DATA[15:0].
normal operation: address output to select the task le
register of an ATA/ATAPI device.
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant
MODE0
DA1[5]
20
I/O
during power-up: input to select the read/write strobe
functionality in generic processor mode; see Table 33 and
0 — Motorola style: pin 26 is R/W and pin 27 is DS
1 — 8051 style: pin 26 is RD and pin 27 is WR
normal operation: address output to select the task le
register of an ATA/ATAPI device
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant
DA2[5]
21
O
address output to select the task le register of an
CMOS output; 5 ns slew rate control
Table 2:
Pin description for LQFP64 …continued
Symbol[1]
Pin
Type[2]
Description
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