參數(shù)資料
型號: 935268625518
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 62/82頁
文件大?。?/td> 1965K
代理商: 935268625518
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
65 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
14.3.3
MDMA mode
Table 79:
GDMA slave mode timing parameters
VCC = 4.0 to 5.5 V; VGND =0V; Tamb = 40 to +85 °C.
Symbol
Parameter
Min
Max
Unit
Tcy1
read/write cycle time
78
-
ns
tsu1
DREQ set-up time before rst DACK on
10
-
ns
td1
DREQ on delay after last strobe off
33.33
-
ns
th1
DREQ hold time after last strobe on
0
53
ns
tw1
DIOR/DIOW pulse width
39
600
ns
tw2
DIOR/DIOW recovery time
36
-
ns
td2
read data valid delay after strobe on
-
20
ns
th2
read data hold time after strobe off
-
5
ns
th3
write data hold time after strobe off
1
-
ns
tsu2
write data set-up time before strobe off
10
-
ns
tsu3
DACK setup time before DIOR/DIOW
assertion
0-
ns
ta1
DACK de-assertion after DIOR/DIOW
de-assertion
030
ns
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 27. MDMA master mode timing.
(write) DATA[15:0]
(read) DATA[15:0]
DREQ (2)
DACK(1)
DIOR/DIOW(1)
tw1
tw2
tsu1
tsu2
td2
tsu2
th1
th2
th3
Tcy1
MGT506
td1
td3
Table 80:
MDMA mode timing parameters
VCC = 4.0 to 5.5 V; VGND =0V; Tamb = 40 to +85 °C.
Symbol
Parameter
Mode 0
Mode 1
Mode 2
Unit
Tcy1(min)
read/write cycle time (minimum)[1]
480
150
120
ns
tw1(min)
DIOR/DIOW pulse width (minimum)[1]
215
80
70
ns
td1(max)
data valid delay after DIOR on
(maximum)
150
60
50
ns
th3(min)
data hold time after DIOR off (minimum)
555ns
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