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參數(shù)資料
| 型號(hào)： | 935268625518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 40/82頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625518 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
45 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.5.5
Test Mode register (address: 84H)
This 1-byte register allows the rmware to set the (D
+, D) lines to predetermined
states for testing purposes. The bit allocation is given in Table 65.
Remark: Only one bit can be set at a time.
[1]
Either FORCEHS or FORCEFS should be set to logic 1 at a time.
[2]
Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit must be set to logic 1 at a
time.
10. Power supply
The ISP1581 can be powered from 3.3 V or 5.0 V.
If the ISP1581 is powered from VCC = 5.0 V, an integrated voltage regulator provides
a 3.3 V supply voltage for the internal logic and the USB transceiver. For connection
details, see Figure 4.
The ISP1581 can also be operated from VCC = 3.3 V. In this case, the internal
regulator is disabled and all the supply pins are connected to VCC. For connection
details see Figure 5.
Table 64:
Scratch Information register: bit description
Bit
Symbol
Description
15 to 8
SFIRH[7:0]
scratch rmware information register (high byte)
7 to 0
SFIRL[7:0]
scratch rmware information register (low byte)
Table 65:
Test Mode register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
FORCEHS
reserved
FORCEFS
PRBS
KSTATE
JSTATE
SE0_NAK
Reset
0
-
00000
Bus reset
0
-
00000
Access
R/W
Table 66:
Test Mode Register: bit description
Bit
Symbol
Description
7[1]
FORCEHS
A logic 1 forces the hardware to high-speed mode only and
disables the chirp detection logic.
6 to 5
-
reserved.
4[1]
FORCEFS
A logic 1 forces the physical layer to full-speed mode only and
disables the chirp detection logic.
3[2]
PRBS
A logic 1 sets the (D
+, D) lines to toggle in a pre-determined
random pattern.
2[2]
KSTATE
Writing a logic 1 sets the (D
+, D) lines to the K state.
1[2]
JSTATE
Writing a logic 1 sets the (D
+, D) lines to the J state.
0[2]
SE0_NAK
Writing a logic 1 sets the (D
+, D) lines to a HS quiescent state.
The device only responds to a valid HS IN token with a NAK.
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