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參數(shù)資料
| 型號： | 935264533557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | SOT-317, MQFP-100 |
| 文件頁數(shù)： | 42/43頁 |
| 文件大小： | 254K |
| 代理商： | 935264533557 |
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1999 March 01
8
Philips Semiconductors
Product specication
Single chip DVB-C channel receiver
VES1820X
SYMBOL
PIN NUMBER
TYPE
DESCRIPTION
IICDIV[1:0]
21,22
I
IICDIV[1:0] allow to select the frequency of the I2C internal system
clock, depending on the crystal frequency. Internal I2C clock is a
division of XIN by 2
IICDIV and must be between 6 and 20 MHz.
SADDR[1:0]
23,24
I
SADDR[1:0] are the 2 LSBs of the I2C address of the VES1820X.
The MSBs are internally set to 00010. Therefore the complete I2C
address of the VES1820X is (MSB to LSB) : 0, 0, 0, 1, 0, SADDR[1],
SADDR[0].
SDA
26
I/O
(5V)
SDA is a bidirectional signal. It is the serial input/output of the I2C
internal block. A pull-up resistor (typically 4.7 k
) must be connected
between SDA and VDD for proper operation (Open Drain output).
SCL
25
I
I2C clock input. SCL should nominally be a square wave with a
maximum frequency of 400KHz. SCL is generated by the system I2C
master.
TEST
19
I
Test input pin. For normal operation of the VES1820X, TEST must
be grounded.
TRST
35
I
Test ReSeT. This active low input signal is used to reset the TAP
controller when in boundary scan mode. In normal mode of operation
TRST must be set low.
TDO
37
O
(5V)
Test Data Out. This is the serial Test output pin used in boundary
scan mode. Serial Data are provided on the falling edge of TCK.
TCK
33
I
Test ClocK : an independant clock used to drive the TAP controller
when in boundary scan mode. In normal mode of operation, TCK
must be grounded.
TDI
34
I
Test Data In. The serial input for Test data and instruction when in
boundary scan mode. In normal mode of operation, TDI must be set
to GND.
TMS
36
I
Test Mode Select. This input signal provides the logic levels needed
to change the TAP controller from state to state. In normal mode of
operation, TMS must be set to VDD.
CTRL1
31
I/O
(5V)
CTRL1 is equivalent to SDA I/O of VES1820X but can be tri-stated
by I2C programmation. It is actually the output of a switch controlled
by parameter BYPIIC of register TEST (index 0F
16). CTRL1 is open
drain output, and therefore requires an external pull up resistor.
CTRL2
32
O
(5V)
CTRL2 can be configured to be a control line output or to output SCL
input. This is controlled by parameter BYPIIC of register TEST (index
0F
16).
CTRL2 is an open drain output and therefore requires an
external pull up resistor.
IT
38
O
(5V)
InTerrupt line. This active low output interrupt line can be configured
by the I2C interface. See registers ITsel (index 32
16)
and ITstat
(index 33
16).
IT is an open drain output and therefore requires an
external pull up resistor.
FEL
39
O
(5V)
By default FEL is a front-end lock indicator. In this case FEL is an
open drain output and therefore requires an external pull up resistor.
But FEL can also be configured to output a PWM signal, which value
can be programmed through the I2C interface (see register
PWMREF, index 34
16).
VIP
92
I
Positive input to the A/D converter. This pin is DC biased to half-
supply through an internal resistor divider (2 x 10k
resistors). In
order to remain in the range of the ADC, the voltage difference
between pins VIP and VIM should be between -0.5 and 0.5 volts.
VIM
91
I
Negative input to the A/D converter. This pin is DC biased to half-
supply through an internal resistor divider (2 x 10k
resistors). In
order to remain in the range of the ADC, the voltage difference
between pins VIP and VIM should be between -0.5 and 0.5 volts.
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