
1999 March 01
32
Philips Semiconductors
Product specication
Single chip DVB-C channel receiver
VES1820X
BOUNDARY SCAN
VES1820X implements a boundary scan architecture to allow access to, and control of, board test support features
within integrated circuits through a Test Access Port (TAP). The TAP controller is a synchronous state machine that
controls the sequence operations on the TAP circuitry when the Test Mode Select (TMS) signal changes. All state
transitions occur on the basis of the TMS value on the rising edge of Test ClocK (TCK). The instruction register is a
shift-register based design. It decodes the test to be performed and/or the test data register to be accessed. The
instructions are shifted into the register through the Test Data Input (TDI) and are latched as the current instruction
at the completion of the shifting process. The VES1820X implemented boundary scan architecture includes : a TAP
controller, a scannable instruction register and three scannable test data registers : a boundary scan register, a
device ID register, and a bypass register (see FIGURE 14 page 32 ).
The supported instructions are : EXTEST, SAMPLE, IDCODE, and BYPASS.
CELLS : Input cells are "observe-only" type and output cells are "observe and control" type.
ID number : It is included in a 32-bit identification register which is included in the scan register itself (first 32-bit of
scan register). It contains a fixed value which identifies the chip.
ID number structure is :
ID version :
’H1
ID part number :
’H1820
ID manufacturer :
’HAB
IDCODE :
’H11820157
SCAN Register : It is composed of 61 cells. Each cell is associated either to an input, three-state output,
bidirectional pad or to the bidirectional or three-state command itself.
FIGURE 14 : BOUNDARY SCAN BLOCK DIAGRAM
TDI
TCK
TRST
TMS
TDO
BOUNDARY SCAN
REGISTER
DEVICE ID REGISTER
BYPASS
REGISTER
CONTROL
INSTRUCTION
MUX FF
SELECT
3-STATE ENABLE
TEST
ACCESS
PORT
CONTROLLER
INSTRUCTION
DECODE
REGISTER
MUX.