參數(shù)資料
型號(hào)： 935263294551
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44
封裝： 10 X 10 X 1.75 MM, PLASTIC, QFP-44
文件頁(yè)數(shù)： 47/48頁(yè)
文件大小： 324K
代理商： 935263294551
Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
8
PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL)
SYMBOL
PIN
TYPE
NAME AND FUNCTION
I/M
I
Bus Configuration: When high or not connected configures the bus interface to the Conditions shown in this table.
D0–D7
I/O
Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the DUART and the
CPU. D0 is the least significant bit.
CEN
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on
D0–D7 as controlled by the WRN, RDN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State
condition.
WRN
I
Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The
transfer occurs on the rising edge of the signal.
RDN
I
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the
data bus. The read cycle begins on the falling edge of RDN.
A0–A3
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET
I
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,
stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark
(High) state. Sets MR pointer to MR1. See Figure 4
INTRN
O
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable
interrupting conditions are true. This pin requires a pullup device.
X1/CLK
I
Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a
crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).
X2
O
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin
to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.
RxDA
I
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.
RxDB
I
Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.
TxDA
O
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark”
condition when the transmitter is disabled, idle or when operating in local loop back mode. “Mark” is High; “space” is Low.
TxDB
O
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’
condition when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is Low.
OP0
O
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated
automatically on receive or transmit.
OP1
O
Output 1: General-purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated
automatically on receive or transmit.
OP2
O
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock output.
OP3
O
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter 1X clock
output, or Channel B receiver 1X clock output.
OP4
O
Output 4: General purpose output or Channel A open-drain, active-Low, RxA interrupt ISR[1] output.
OP5
O
Output 5: General-purpose output or Channel B open-drain, active-Low, RxB interrupt ISR[5] output.
OP6
O
Output 6: General purpose output or Channel A open-drain, active-Low, TxA interrupt ISR[0] output.
OP7
O
Output 7: General-purpose output, or Channel B open-drain, active-Low, TxB interrupt ISR[4] output.
IP0
I
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN).
IP1
I
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN).
IP2
I
Input 2: General-purpose input or counter/timer external clock input.
IP3
I
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP4
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock.
IP5
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP6
I
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock.
VCC
Pwr
Power Supply: +3.3 or +5V supply input
±10%
GND
Pwr
Ground
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