參數(shù)資料
型號(hào)： 935263294551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44
封裝： 10 X 10 X 1.75 MM, PLASTIC, QFP-44
文件頁數(shù)： 27/48頁
文件大?。?/td> 324K
代理商： 935263294551
Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
33
ISR—Interrupt Status Register
This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR).
If a bit in the ISR is a ‘1’ and the corresponding bit in the IMR is also a ‘1’, the INTRN output will be asserted (Low). If the corresponding bit in
the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR - the
true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to H‘00’ when the DUART is reset.
ISR INTERRUPT STATUS REGISTER
Addr
Bit 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ISR
INPUT
PORT
CHANGE
DELTA
Break B
RxRDY/
FFULL B
TxRDY B
Counter
Ready
Delta
Break A
RxRDY/
FFULL A
TxRDY A
0x05
0 = not active
0 = not active
0 = not active
0 = not active
0 = not active
0 = not active
0 = not active
0 = not active
1 = active
1 = active
1 = active
1 = active
1 = active
1 = active
1 = active
1 = active
ISR[7]—Input Port Change Status
This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,
IP2, or IP3 inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
the CPU reads the IPCR.
ISR[6]—Channel B Change In Break
This bit, when set, indicates that the Channel B receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel B ‘reset break change interrupt’
command.
ISR[5]—RxB Interrupt
This bit indicates that the channel B receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.
ISR[4]—TxB Interrupt
This bit indicates that the channel B transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.
ISR[3]—Counter Ready.
In the counter mode, this bit is set when the counter reaches
terminal count and is reset when the counter is stopped by a stop
counter command.
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time that the counter/timer reaches zero
count). The bit is reset by a stop counter command. The command,
however, does not stop the counter/timer.
ISR[2]—Channel A Change in Break
This bit, when set, indicates that the Channel A receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel A ‘reset break change interrupt’
command.
ISR[1]—RxA Interrupt
This bit indicates that the channel A receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.
ISR[0]—TxA Interrupt
This bit indicates that the channel A transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.
IMR—Interrupt Mask Register
The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the ISR is a ‘1’ and the corresponding bit in
the IMR is also a ‘1’ the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect
on the INTRN output. Note that the IMR does not mask the programmable interrupt outputs OP3–OP7 or the reading of the ISR.
IMR INTERRUPT MASK REGISTER
Addr
Bit 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IMR
INPUT
PORT
CHANGE
Delta
Break B
RxRDY/
FFULL B
TxRDY B
Counter
Ready
Delta
Break A
RxRDY/
FFULL A
TxRDY
A
0 = not
enabled
0 = not
enabled
0 = not
enabled
0 = not
enabled
0 = not
enabled
0 = not
enabled
0 = not
enabled
0 = not
enabled
1 = enabled
1 = enabled
1 = enabled
1 = enabled
1 = enabled
1 = enabled
1 = enabled
1 = enabled
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