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參數(shù)資料
| 型號： | 935263294551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大?。?/td> | 324K |
| 代理商： | 935263294551 |
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Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
14
AC CHARACTERISTICS (3.3 VOLT) 1, 2, 3
VCC = 3.3V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.
LIMITS4
SYMBOL
PARAMETER
Min
Typ
Max
UNIT
Reset Timing (See Figure 4)
tRES
Reset pulse width
100
20
ns
Bus Timing5 (See Figure 5)
t*AS
A0–A3 setup time to RDN, WRN Low
10
6
ns
t*AH
A0–A3 hold time from RDN, WRN low
25
16
ns
t*CS
CEN setup time to RDN, WRN low
0
ns
t*CH
CEN Hold time from RDN. WRN low
0
ns
t*RW
WRN, RDN pulse width (Low time)
20
10
ns
t*DD
Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)
46
75
ns
t*DA
RDN low to data bus active6
0
ns
t*DF
Data bus floating after RDN or CEN high
15
20
ns
t*DI
RDN or CEN high to data bus invalid7
0
ns
t*DS
Data bus setup time before WRN or CEN high (write cycle)
25
20
ns
t*DH
Data hold time after WRN high
0
–15
ns
t*RWD
High time between read and/or write cycles5, 7
20
10
ns
Port Timing5 (See Figure 9)
t*PS
Port in setup time before RDN low (Read IP ports cycle)
0
–20
ns
t*PH
Port in hold time after RDN high
0
–20
ns
t*PD
OP port valid after WRN or CEN high (OPR write cycle)
50
70
ns
Interrupt Timing (See Figure 10)
t*IR
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RxFIFO (RxRDY/FFULL interrupt)
40
60
ns
Write TxFIFO (TxRDY interrupt)
40
60
ns
Reset Command (delta break change interrupt)
40
60
ns
Stop C/T command (Counter/timer interrupt
40
60
ns
Read IPCR (delta input port change interrupt)
40
60
ns
Write IMR (Clear of change interrupt mask bit(s))
40
60
ns
Clock Timing (See Figure 11)
t*CLK
X1/CLK high or low time
30
25
ns
f*CLK
X1/CLK frequency8
0.1
3.686
8
MHz
f*CTC
C/T Clk (IP2) high or low time (C/T external clock input)
30
15
ns
f*CTC
C/T Clk (IP2) frequency8
0
8
MHz
t*RX
RxC high or low time (16X)
30
10
ns
f*RX
RxC Frequency (16X)
0
16
MHz
RxC Frequency (1x)8, 9
0
1
MHz
t*TX
TxC High or low time (16X)
30
15
ns
f*TX
TxC frequency (16X)
16
MHz
TxC frequency (1X)8, 9
0
1
MHz
Transmitter Timing, external clock (See Figure 12)
t*TXD
TxD output delay from TxC low (TxC input pin)
40
60
ns
t*TCS
Output delay from TxC output pin low to TxD data output
8
30
ns
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