參數(shù)資料
型號： 935260577557
廠商： NXP SEMICONDUCTORS
元件分類： 無繩電話/電話
英文描述： TELECOM, CORDLESS, BASEBAND CIRCUIT, PQFP100
封裝： PLASTIC, SOT-407, LQFP-100
文件頁數(shù)： 57/59頁
文件大?。?/td> 781K
代理商： 935260577557
1999 Jun 04
7
Philips Semiconductors
Product specication
Global Positioning System (GPS)
baseband processor
SAA1575HL
A11
24
O
External memory address bus bit 11: 19-bit address bus; used to address external
RAM and program memory
VCC(P)
25
Main I/O power supply: 2.7 to 5.5 V operating range; main supply for the periphery
in normal operation
VSS
26
Ground: 0 V reference
A10
27
O
External memory address bus bit 10: 19-bit address bus; used to address external
RAM and program memory
A9
28
O
External memory address bus bit 9: 19-bit address bus; used to address external
RAM and program memory
A8
29
O
External memory address bus bit 8: 19-bit address bus; used to address external
RAM and program memory
VCC(core)
30
Main core power supply: 2.7 to 3.6 V only; main supply for the core in normal
operation
VSS
31
Ground: 0 V reference
A7
32
O
External memory address bus bit 7: 19-bit address bus; used to address external
RAM and program memory
A6
33
O
External memory address bus bit 6: 19-bit address bus; used to address external
RAM and program memory
A5
34
O
External memory address bus bit 5: 19-bit address bus; used to address external
RAM and program memory
A4
35
O
External memory address bus bit 4: 19-bit address bus; used to address external
RAM and program memory
A3
36
O
External memory address bus bit 3: 19-bit address bus; used to address external
RAM and program memory
VCC(P)
37
Main I/O power supply: 2.7 to 5.5 V operating range; main supply for the periphery
in normal operation
VSS
38
Ground: 0 V reference
A2
39
O
External memory address bus bit 2: 19-bit address bus; used to address external
RAM and program memory
A1
40
O
External memory address bus bit 1: 19-bit address bus; used to address external
RAM and program memory
PMCS
41
O
External program memory select: external program memory read strobe
TP2
42
I
Test pin: tie LOW
RSTIME
43
I
Reset timer control: this controls the on-chip reset timer. If this is HIGH, reset will be
de-asserted approximately 10 ms after both PWRDN and PWRFAIL go HIGH. If this
is LOW, reset will be de-asserted approximately 10
s after both
PWRDN and PWRFAIL go HIGH.
TP1
44
I
Test pin: tie LOW
WRH
45
I/O
Write MSB: write strobe for external data memory; asserted for both MSB and word
write operations; input mode only used for test purposes
WRL
46
I/O
Write LSB: write strobe for external data memory; asserted for both LSB and word
write operations; input mode only used for test purposes
RD
47
I/O
External data read: read strobe for external data memory; input mode only used for
test purposes
SYMBOL
PIN
I/O
DESCRIPTION
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