參數(shù)資料
型號(hào)： 935260577557
廠商： NXP SEMICONDUCTORS
元件分類： 無(wú)繩電話/電話
英文描述： TELECOM, CORDLESS, BASEBAND CIRCUIT, PQFP100
封裝： PLASTIC, SOT-407, LQFP-100
文件頁(yè)數(shù)： 24/59頁(yè)
文件大?。?/td> 781K
代理商： 935260577557
1999 Jun 04
30
Philips Semiconductors
Product specication
Global Positioning System (GPS)
baseband processor
SAA1575HL
11 AC CHARACTERISTICS
VCC(P) =VCC(B) =5V; VCC(core) =VCC(R) =3V; Tamb =20 °C; fosc = 30 MHz; standard Philips rmware (release HD00);
unless otherwise specied.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
External clock
fosc
oscillator frequency
26
30
32
MHz
Tclk
clock period and CPU timing cycle
33.3
ns
tCLKH
clock HIGH time
40 to 60% duty cycle
6.7
ns
tCLKL
clock LOW time
40 to 60% duty cycle
6.7
ns
tr(clk)
clock rise time
5
ns
tf(clk)
clock fall time
5
ns
fclk(ref)
reference clock frequency
14.4
35
MHz
External program memory read (non-burst code read); see Fig.16
tAVAU
address valid time period
163.7
165.7
ns
tAVPL
address valid to PMCS asserted
62.7
65.7
ns
tW(PMCS)
PMCS pulse width
97.0
98.0
ns
tPLIV
PMCS LOW to instruction valid
82.0
85.0
ns
th(I)
instruction hold time after PMCS de-asserted
0.0
ns
tAVIV
address valid to instruction valid (access time)
148.7
151.7
ns
tsu(I)
instruction set-up time before PMCS
de-asserted
14.0
16.0
ns
tPXIZ
bus 3-state after PMCS de-asserted
30.0
36.0
ns
th
hold time of a (3 : 1) after PMCS de-asserted
0.0
1.0
ns
External program memory read (burst code read); see Figs 16 and 17
tAVAU
address valid time period
131.3
132.3
ns
tAVIV
address valid to instruction valid (access time)
115.3
118.3
ns
tIVAU
instruction valid to address undened
15.0
17.0
ns
tAUIU
address valid to instruction undened
0.0
ns
External data memory read; see Fig.18
tAVAU
address valid time period
163.7
164.7
ns
tRLEL
RD asserted to DMCS asserted
note 1
2.0
4.0
ns
tW(DMCS)
DMCS pulse width
97.0
98.0
ns
tRHEH
RD de-asserted to DMCS de-asserted
2.0
6.0
ns
tAVRL
address valid to RD asserted
64.7
65.7
ns
tW(RD)
RD pulse width
98.0
ns
tAVDV
address valid to data valid (access time)
148.7
151.7
ns
tRLDV
RD asserted to data valid
82.0
85.0
ns
tsu(D)
data set-up time before RD de-asserted
15.0
16.0
ns
th(D)
data hold time after RD de-asserted
0.0
ns
tRHDZ
bus 3-state after RD de-asserted
30.0
36.0
ns
相關(guān)PDF資料
PDF描述
935260580118 LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
935260608112 TELEPHONE MULTIFUNCTION CKT, PDSO28
935260608118 TELEPHONE MULTIFUNCTION CKT, PDSO28
935260687112 TELEPHONE MULTIFUNCTION CKT, PDSO28
935260687118 TELEPHONE MULTIFUNCTION CKT, PDSO28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
935261069122 制造商:NXP Semiconductors 功能描述:IC SECURITY TRANSPONDER PLLMC
935262025112 制造商:NXP Semiconductors 功能描述:SUB ONLY IC
935262217118 制造商:NXP Semiconductors 功能描述:Real Time Clock Serial 8-Pin SO T/R
935264217557 制造商:NXP Semiconductors 功能描述:SUB ONLY IC
935267356112 制造商:NXP Semiconductors 功能描述:IC TEA1507PN
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*