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參數(shù)資料
| 型號： | 935260577557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CORDLESS, BASEBAND CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, SOT-407, LQFP-100 |
| 文件頁數(shù)： | 54/59頁 |
| 文件大小： | 781K |
| 代理商： | 935260577557 |
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1 power-down/reset controller.
The structure is based on a 16-bit microcontroller core operating on all other units as memory mapped peripherals and registers. A 16-bit
data bus and a 19-bit address bus are extended to external pins so that external data and program memory can be accessed. On-chip
decoder circuits eliminate the need for external glue logic for external memory access.
Each of the 8 GPS channel correlators includes a carrier Numerically Controlled Oscillator (NCO), PN code generator, phase rotator and
low-pass filter. They correlate the local PN sequence with the digitized input GPS signal and generate the filtered correlation result for the
microcontroller. The firmware provided then generates a navigation solution and provides standard GPS data outputs to the user.
The GPS firmware is located in off-chip program memory. It processes the GPS signals from up to 8 satellites and generates GPS
information that can be output to the host processor through one of the two serial ports. Much of hardware configuration of the SAA1575HL
can be controlled by the firmware and so details such as the external bus timing may change between firmware revisions. For the purpose
of this document, the standard Philips firmware has been assumed (release HD00).
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Single-chip GPS baseband solution with built-in 16-bit microcontroller
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All digital, 0.5 micron CMOS technology
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Single power supply with full 3 V operation
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Separate I/O power supply pins for operation with 3 or 5 V external devices
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Up to 30 MHz system clock from on-chip crystal oscillator or external clock input
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2 kbytes words internal data memory for fast execution
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External bus for up to 512 kbytes words data memory and 512 kbytes words program memory
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Programmable external bus timing to match external memory speed
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Chip selection outputs to reduce glue logic requirements
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Reset controller for power-down detection and servicing
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8 GPS channel correlators driven by firmware for flexible GPS correlation algorithms
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1 second pulse output of GPS time
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2-bit digital IF GPS signal input synchronized to external sample clock
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2 fully duplex UARTs for communication with host system processor and other devices
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Real-time clock with 32.768 kHz crystal and supply for low power timekeeping
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Watchdog timer
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Power-down modes under firmware control
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100-pin LQFP package
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50 mA supply current (typ.) when 8 GPS channels in track (approximate).
Features
Datasheet
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