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參數(shù)資料
| 型號： | 935260577557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CORDLESS, BASEBAND CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, SOT-407, LQFP-100 |
| 文件頁數(shù)： | 15/59頁 |
| 文件大?。?/td> | 781K |
| 代理商： | 935260577557 |
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1999 Jun 04
22
Philips Semiconductors
Product specication
Global Positioning System (GPS)
baseband processor
SAA1575HL
7.8.2.2
Example of strategy for slow supplies
The ultimate use of the power control signals is up to the
user. However, two possibilities are presented as design
examples. The first example will operate correctly in
circuits where the rise times of the power supplies is slow
compared to any delay between the supplies to the
peripheral and core power domains.
In this example, both the PWRDN and PWRFAIL logic
inputs to the SAA1575HL are derived by comparing the
VCC(P) supply voltage against known references.
In general, since it is a lower voltage, the VCC(core) supply
may hold and reach it’s nominal voltage quicker than the
VCC(P) supply.
As VCC(P) falls, the first threshold is reached and PWRDN
is taken LOW. This triggers an interrupt in the firmware
which is used to perform any required housekeeping. It is
assumed that there is time for this to be completed before
complete supply failure.
At the end of the interrupt routine, the firmware places the
SAA1575HL into reset. As VCC(P) continues to fall, the
second threshold is reached and is taken LOW. This
toggles the power controls, both PWRM and PWRB, and
will force a reset if it has not already occurred.
On power-up, the power controls both PWRM and PWRB
will be switched once the second threshold voltage is
reached. As the supply voltage rises further, the first
voltage threshold will be reached at which time both
PWRDN and PWRFAIL will be HIGH. This starts the reset
counter and the SAA1575HL will remain in reset until a set
time after this, depending on the state of the input pin
RSTIME.
Fig.11 Example of power-down strategy with slow supplies.
handbook, full pagewidth
MHB470
PWRB
delay while XA in
interrupt routine
reset timer delay
set by RSTIME
Vt1
VCC(P)
VCC(core)
Vt2
PWRFAIL
PWRDN
PWRM
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