參數(shù)資料
型號(hào): 89C61X2
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 80C51 8-bit Flash microcontroller family
中文描述: 80C51的8位閃存微控制器系列
文件頁(yè)數(shù): 48/56頁(yè)
文件大?。?/td> 342K
代理商: 89C61X2
Philips Semiconductors
Product data
P89C60X2/61X2
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
2003 Sep 11
48
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE)
T
amb
= 0
°
C to +70
°
C; V
CC
= 5 V
±
10%, V
SS
= 0 V
1, 2, 3
SYMBOL
FIGURE
PARAMETER
VARIABLE CLOCK
4
MIN
0
t
CLCL
–40
0.5t
CLCL
–20
0.5t
CLCL
–20
20 MHz CLOCK
4
MIN
MAX
20
MAX
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
35
31
31
31
31
31
31
31
31
31
31
31
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
10
5
5
2t
CLCL
–65
35
0.5t
CLCL
–20
1.5t
CLCL
–45
5
30
1.5t
CLCL
–60
15
0
0
0.5t
CLCL
–20
2.5t
CLCL
–80
10
5
45
10
32
33
32
32
32
32
32
32, 33
32, 33
33
33
33
32
32, 33
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
3t
CLCL
–100
3t
CLCL
–100
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.5t
CLCL
–90
35
0
0
t
CLCL
–20
4t
CLCL
–150
4.5t
CLCL
–165
1.5t
CLCL
+50
5
50
60
125
1.5t
CLCL
–50
2t
CLCL
–75
0.5t
CLCL
–25
0.5t
CLCL
–20
3.5t
CLCL
–130
25
25
0
5
45
0
0.5t
CLCL
+20
0
45
0.5t
CLCL
–20
5
35
35
35
35
High time
Low time
Rise time
Fall time
20
20
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
5
5
ns
ns
ns
ns
34
34
34
34
34
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
6t
CLCL
5t
CLCL
–133
t
CLCL
–30
0
300
117
20
0
ns
ns
ns
ns
ns
5t
CLCL
–133
117
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