參數(shù)資料
型號(hào)： 89C61X2
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： 80C51 8-bit Flash microcontroller family
中文描述： 80C51的8位閃存微控制器系列
文件頁(yè)數(shù)： 42/56頁(yè)
文件大小： 342K
代理商： 89C61X2
Philips Semiconductors
Product data
P89C60X2/61X2
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
2003 Sep 11
42
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Table 10. Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
N (L)
1
VECTOR ADDRESS
External interrupt 0
1
IE0
Y (T)
2
03H
Timer 0
2
TF0
Y
0BH
External interrupt 1
3
IE1
N (L)
Y (T)
13H
Timer 1
4
TF1
Y
1BH
UART
5
RI, TI
N
23H
Timer 2
6
TF2, EXF2
N
2BH
NOTES:
1. L = Level activated
2. T = Transition activated
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output, unless the CPU needs to perform an off-chip memory
access.
AUXR (8EH)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
EXTRAM
AO
AUXR.0
AUXR.1
AO
EXTRAM
Turns off ALE output.
Controls external data memory
access.
Dual DPTR
The dual DPTR structure (see Figure 28) enables a way to specify
the address of an external data memory location. There are two
16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1/bit0 that allows the program code to
switch between them.
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxx000x0B
AUXR1 (A2H)
7
6
5
4
3
2
1
0
–
–
–
–
GF2
0
–
DPS
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg
DPS
DPTR0
DPTR1
0
1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
The GF2 bit is a general purpose user-defined flag.
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an INC
AUXR1 instruction without affecting the GF2 bit.
DPS
DPTR1
DPTR0
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
SU00745A
BIT0
AUXR1
Figure 28.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
MOV DPTR, #data16
Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR
Move code byte relative to DPTR to ACC
MOVX A, @ DPTR
Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A
Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR
Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
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