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參數(shù)資料
| 型號： | 8400110EKILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, QCC32 |
| 封裝： | 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 699K |
| 代理商： | 8400110EKILF |
ICS8400110I Data Sheet
LOW JITTER, TELCOM RATE-CONVERSION PLL
ICS8400110EKI REVISION A NOVEMBER 9, 2009
10
2009 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8400110I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8400110I is the sum of the core power plus the analog power plus the power dissipation in the load(s).
The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.6V *(130mA + 15mA) = 522mW
Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.6V / [2 * (50 + 17)] = 26.9mA
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)
2 = 17
* (26.9mA)2 = 12.3mW per output
Total Power Dissipation on the ROUT
Total Power (ROUT) = 12.3mW * 2 = 24.6mW
Total Power Dissipation
Total Power
= Power (core)MAX + Total Power (ROUT)
= 522mW + 24.6mW
= 546.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.547W *37°C/W = 105.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection
θ
JA by Velocity
Meters per Second
01
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
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