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參數(shù)資料
| 型號： | 843002AKI-40LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 175 MHz, OTHER CLOCK GENERATOR, QCC32 |
| 封裝： | 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 742K |
| 代理商： | 843002AKI-40LF |
175MHZ, FEMTOCLOCKTM VCXO BASED
SONET/SDH JITTER ATTENUATOR
ICS843002I-40
IDT / ICS VCXO BASED SONET/SDH JITTER ATTENUATOR
1
ICS843002AKI-40 REV. B APRIL 27, 2009
General Description
The ICS843002I-40 is a member of the
HiperClockSfamily of high performance clock
solutions from IDT. The ICS843002I-40 is a PLL
based synchronous clock generator that is
optimized for SONET/SDH line card applications
where jitter attenuation and frequency translation is needed. The
device contains two internal PLL stages that are cascaded in
series. The first PLL stage uses a VCXO which is optimized to
provide reference clock jitter attenuation and to be jitter tolerant,
and to provide a stable reference clock for the 2nd PLL stage
(typically 19.44MHz). The second PLL stage provides additional
frequency multiplication (x32), and it maintains low output jitter by
using a low phase noise FemtoClock VCO. PLL multiplication
ratios are selected from internal lookup tables using device input
selection pins. The device performance and the PLL multiplication
ratios are optimized to support non-FEC (non-Forward Error
Correction) SONET/SDH applications with rates up to OC-48
(SONET) or STM-16 (SDH). The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the PLL
loop bandwidth and damping characteristics for the given line card
application.
The ICS843002I-40 includes two clock input ports. Each one can
accept either a single-ended or differential input. Each input port
also includes an activity detector circuit, which reports input clock
activity through the LOR0 and LOR1 logic output pins. The two
input ports feed an input selection mux. “Hitless switching” is
accomplished through proper filter tuning. Jitter transfer and
wander characteristics are influenced by loop filter tuning, and
phase transient performance is influenced by both loop filter
tuning and alignment error between the two reference clocks.
Typical ICS843002I-40 configuration in SONET/SDH Systems:
VCXO 19.44MHz crystal
Loop bandwidth: 50Hz - 250Hz
Input Reference clock frequency selections:
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,
622.08MHz
Output clock frequency selections:
19.44MHz, 77.76MHz, 155.52MHz, Hi-Z
Features
Two Differential LVPECL outputs
Selectable CLKx, nCLKx differential input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or
single-ended LVCMOS or LVTTL levels
Maximum output frequency: 175MHz
FemtoClock VCO frequency range: 560MHz - 700MHz
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 0.81ps (typical)
Full 3.3V or mixed 3.3V core/2.5V output operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
ICS843002I-40
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
HiPerClockS
ICS
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
LF1
LF0
ISET
VCC
CLK0
nCLK0
CLK_SEL
nc
LOR0
LOR1
nc
VCCO_LVCMOS
VCCO_LVPECL
nQB
QB
VEE
QA_SEL1
QA_SEL0
nc
QB_SEL1
QB_SEL0
V
CCA
QA
nQA
XTAL_OUT
R_SEL2
R_SEL1
R_SEL0
V
EE
CLK1
nCLK1
XTAL_IN
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 843002AKI-40LFT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 843002AKI-40T | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| 843002AKI-41 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| 843002AKI-41LF | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 843002AKI-41LFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Generator Dual 32-Pin VFQFPN EP T/R 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK GEN DUAL 32PIN VFQFPN - Tape and Reel |
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