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參數(shù)資料
| 型號： | 8400110EKILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, QCC32 |
| 封裝： | 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 699K |
| 代理商： | 8400110EKILF |
ICS8400110I Data Sheet
LOW JITTER, TELCOM RATE-CONVERSION PLL
ICS8400110EKI REVISION A NOVEMBER 9, 2009
8
2009 Integrated Device Technology, Inc.
Crystal Input Interface
The ICS8400110I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in Figure
2 below were determined using a 25MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The OSCi input can accept a single-ended LVCMOS signal through
an AC coupling capacitor. A general interface diagram is shown in
Figure 3. The OSCo pin can be left floating. The input edge rate can
be as slow as 10ns. For LVCMOS signals, it is recommended that the
amplitude be reduced from full swing to half swing in order to prevent
signal interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver (Ro)
plus the series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two ways.
First, R1 and R2 in parallel should equal the transmission line
impedance. For most 50
applications, R1 and R2 can be 100. This
can also be accomplished by removing R1 and making R2 50
. By
overdriving the crystal oscillator, the device will be functional, but
note, the device performance is guaranteed by using a quartz crystal.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
OSCi
OSCo
X1
18pF Parallel Crystal
C1
27p
C2
33p
OSCi
OSCo
Ro
Rs
Zo = Ro + Rs
50
0.1f
R1
R2
VCC
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