
Table 12-30.
CPU to Local Memory----Input Requirements
Symbol
Parameters
Min.
Max.
t120
PARL, PARH setup before PROCCLK rise during read
7
----
t121
PARL, PARH hold after PROCCLK rise during read
5
----
t122
D0-15 setup before PROCCLK rise during read
7
----
t123
D0-15 hold after PROCCLK rise during read
5
----
CPU to AT-Bus, On-Board I/O, and ROM
Tables 12-31 through 12-33 shows the CPU AT bus, on-board I/O, and ROM accesses.
Table 12-31.
CPU to AT-Bus, On-Board I/O, and ROM----Output Responses
Symbol
Parameters
Min.
Max.
t130
LOMEGCS delay from PROCCLK rise
----
35
t131
-NA delay from PROCCLK rise (C
L
= 25pF)
-READY delay from PROCCLK rise
----
15
t132
4
31
t133
ALE rise from BUSCLK low
----
25
t134
ALE fall from BUSCLK high
----
15
t135
Command and -ROMCS active from BUSCLK
----
30
t136
Command and -ROMCS inactive from BUSCLK rise
----
25
t137
MODA0 delay from PROCCLK rise
----
30
t138
MODA0 rise from BUSCLK fall during bus convert
----
20
t139
MODA20 delay from A20 (if MODA20 enabled)
----
35
t140
MODA20 delay from HOLD fall
----
40
t141
SDIRL, H delay from PROCCLK rise
----
50
t142
XD0-15 delay from PROCCLK rise during write
----
50
t143
XD0-15 turn-on delay from PROCCLK rise
5
----
t144
XD0-15 turn-off delay from PROCCLK rise
----
50
t145
XD0-15 delay from D0-15 during CPU write or Master read
----
30
t146
XD0-7 delay from D8-15 during CPU write
(byte swap)
----
70
t147
D0-15 delay from XD0-15 during CPU read or DMA/Master write
----
25
t148
D8-15 delay from XD0-7 during CPU read (byte swap) or DMA
----
40
I
AC Characteristics 25MHz
System Characteristics
12-16
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.