
Table 12-16.
DMA and AT-Bus Master Access to Local Memory----Formula Specifications
16MHz
20MHz
Symbol
Critical Path
Formula
Min.
Max.
Min.
Max.
te230
RAS precharge before refresh
t230-t263-t265
----
27
----
27
te233
MWE rise before CAS fall (read)
t233-t102
----
35
----
24
te235
RAS precharge, Master
t235-t239
----
16
----
16
te239
Master read, access from RAS
t239+t145
----
51
----
51
te240
Row address to RAS
t240-t239+t106
----
25
----
25
te242
Master write, SDIR fall
t242+t147
----
65
----
65
Table 12-17.
DMA and AT-Bus Master Access to Local Memory----Input Requirements
16MHz
20MHz
Symbol
Parameters
Min.
Max.
Min.
Max.
t250
PARL, PARH setup before -XMEMR rise
during mem read
20
----
20
----
t251
PARL, PARH hold after -XMEMR rise
during mem read
0
----
0
----
Refresh
The refresh timing specifications and requirements are shown in Tables 12-18 through
12-20.
Table 12-18.
Refresh----Output Responses
16MHz
20MHz
Symbol
Parameters
Min.
Max.
Min.
Max.
t260
-REFRESH active from HLDA
----
71
----
71
t261
-REFRESH float from OSC2 rise
Refresh address valid from -REFRESH active
----
55
----
55
t262
----
45**
----
45**
t263
-XMEMR active from OSC2 rise
----
60
----
55
t264
-XMEMR inactive from OSC2 rise
----
55
----
50
t265
-RAS0, -RAS3 active from -XMEMR fall
----
35
----
30
t266
-RAS0, -RAS3 inactive from -XMEMR rise
----
30
----
25
t267
-RAS1, -RAS2 active from -XMEMR fall
----
75
----
70
t268
-RAS1, -RAS2 inactive from -XMEMR rise
----
75
----
70
** 40ns maximum for 836A.
Refresh address refers to MODA0, A0-9, and MA0-9.
I
AC Characteristics 16- and 20MHz
System Characteristics
12-10
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.